Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.

--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1

7 files changed, 133 insertions, 12 deletions

diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 0552c282b..81e96a8d6 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -37,18 +37,19 @@ if env['TARGET_ISA'] == 'sparc':
     Source('floatregfile.cc')
     Source('intregfile.cc')
     Source('miscregfile.cc')
+    Source('pagetable.cc')
     Source('regfile.cc')
     Source('remote_gdb.cc')
+    Source('tlb.cc')
     Source('utility.cc')
 
+    SimObject('SparcTLB.py')
+
     if env['FULL_SYSTEM']:
         SimObject('SparcSystem.py')
-        SimObject('SparcTLB.py')
 
-        Source('pagetable.cc')
         Source('stacktrace.cc')
         Source('system.cc')
-        Source('tlb.cc')
         Source('ua2005.cc')
         Source('vtophys.cc')
     else:
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 88c086090..07d332b58 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -620,6 +620,70 @@ void PowerOnReset::invoke(ThreadContext * tc)
 
 #else // !FULL_SYSTEM
 
+void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc)
+{
+    Process *p = tc->getProcessPtr();
+    Addr paddr;
+    bool success = p->pTable->translate(vaddr, paddr);
+    if(!success) {
+        panic("Tried to execute unmapped address %#x.\n", vaddr);
+    } else {
+
+        uint64_t entry = 0;
+        entry |= 0ULL << 1; // Not writable
+        entry |= 0ULL << 2; // Available in nonpriveleged mode
+        entry |= 0ULL << 3; // No side effects
+        entry |= 1ULL << 4; // Virtually cachable
+        entry |= 1ULL << 5; // Physically cachable
+        entry |= 0ULL << 6; // Not locked
+        entry |= mbits(paddr, 39, 13); // Physical address
+        entry |= 0ULL << 48; // size = 8k
+        entry |= 0uLL << 59; // Endianness not inverted
+        entry |= 0ULL << 60; // Not no fault only
+        entry |= 0ULL << 61; // size = 8k
+        entry |= 1ULL << 63; // valid
+        PageTableEntry PTE(entry);
+
+        Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+        tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
+                p->M5_pid /*context id*/, false, PTE);
+    }
+}
+
+void FastDataAccessMMUMiss::invoke(ThreadContext *tc)
+{
+    Process *p = tc->getProcessPtr();
+    Addr paddr;
+    bool success = p->pTable->translate(vaddr, paddr);
+    if(!success) {
+        p->checkAndAllocNextPage(vaddr);
+        success = p->pTable->translate(vaddr, paddr);
+    }
+    if(!success) {
+        panic("Tried to access unmapped address %#x.\n", vaddr);
+    } else {
+
+        uint64_t entry = 0;
+        entry |= 1ULL << 1; // Writable
+        entry |= 0ULL << 2; // Available in nonpriveleged mode
+        entry |= 0ULL << 3; // No side effects
+        entry |= 1ULL << 4; // Virtually cachable
+        entry |= 1ULL << 5; // Physically cachable
+        entry |= 0ULL << 6; // Not locked
+        entry |= mbits(paddr, 39, 13); // Physical address
+        entry |= 0ULL << 48; // size = 8k
+        entry |= 0uLL << 59; // Endianness not inverted
+        entry |= 0ULL << 60; // Not no fault only
+        entry |= 0ULL << 61; // size = 8k
+        entry |= 1ULL << 63; // valid
+        PageTableEntry PTE(entry);
+
+        Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+        tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
+                p->M5_pid /*context id*/, false, PTE);
+    }
+}
+
 void SpillNNormal::invoke(ThreadContext *tc)
 {
     doNormalFault(tc, trapType(), false);
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 2456ad28a..ae16c42fc 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -32,6 +32,7 @@
 #ifndef __SPARC_FAULTS_HH__
 #define __SPARC_FAULTS_HH__
 
+#include "config/full_system.hh"
 #include "sim/faults.hh"
 
 // The design of the "name" and "vect" functions is in sim/faults.hh
@@ -42,6 +43,8 @@ namespace SparcISA
 typedef uint32_t TrapType;
 typedef uint32_t FaultPriority;
 
+class ITB;
+
 class SparcFaultBase : public FaultBase
 {
   public:
@@ -199,9 +202,29 @@ class PAWatchpoint : public SparcFault<PAWatchpoint> {};
 class VAWatchpoint : public SparcFault<VAWatchpoint> {};
 
 class FastInstructionAccessMMUMiss :
-    public SparcFault<FastInstructionAccessMMUMiss> {};
+    public SparcFault<FastInstructionAccessMMUMiss>
+{
+#if !FULL_SYSTEM
+  protected:
+    Addr vaddr;
+  public:
+    FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
+    {}
+    void invoke(ThreadContext * tc);
+#endif
+};
 
-class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss> {};
+class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
+{
+#if !FULL_SYSTEM
+  protected:
+    Addr vaddr;
+  public:
+    FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
+    {}
+    void invoke(ThreadContext * tc);
+#endif
+};
 
 class FastDataAccessProtection : public SparcFault<FastDataAccessProtection> {};
 
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 0edbdec4b..4f3d20606 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -98,12 +98,6 @@ namespace SparcISA
 
     StaticInstPtr decodeInst(ExtMachInst);
 
-#if FULL_SYSTEM
-    // I don't know what it's for, so I don't
-    // know what SPARC's value should be
-    // For loading... XXX This maybe could be USegEnd?? --ali
-    const Addr LoadAddrMask = ULL(0xffffffffff);
-
     /////////// TLB Stuff ////////////
     const Addr StartVAddrHole = ULL(0x0000800000000000);
     const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
@@ -111,6 +105,12 @@ namespace SparcISA
     const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
     const Addr BytesInPageMask = ULL(0x1FFF);
 
+#if FULL_SYSTEM
+    // I don't know what it's for, so I don't
+    // know what SPARC's value should be
+    // For loading... XXX This maybe could be USegEnd?? --ali
+    const Addr LoadAddrMask = ULL(0xffffffffff);
+
     enum InterruptTypes
     {
         IT_TRAP_LEVEL_ZERO,
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index 41a1c2136..29b1a244b 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -121,6 +121,12 @@ Sparc32LiveProcess::startup()
     threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
     //Set the ASI register to something fixed
     threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
+
+    /*
+     * T1 specific registers
+     */
+    //Turn on the icache, dcache, dtb translation, and itb translation.
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
 }
 
 void
@@ -137,7 +143,7 @@ Sparc64LiveProcess::startup()
     threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0);
 
     threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0);
-    //
+
     /*
      * Register window management registers
      */
@@ -163,6 +169,12 @@ Sparc64LiveProcess::startup()
     threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
     //Set the ASI register to something fixed
     threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
+
+    /*
+     * T1 specific registers
+     */
+    //Turn on the icache, dcache, dtb translation, and itb translation.
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
 }
 
 M5_32_auxv_t::M5_32_auxv_t(int32_t type, int32_t val)
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 12891e2b3..edc9d37a9 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -535,7 +535,11 @@ ITB::translate(RequestPtr &req, ThreadContext *tc)
         if (real)
             return new InstructionRealTranslationMiss;
         else
+#if FULL_SYSTEM
             return new FastInstructionAccessMMUMiss;
+#else
+            return new FastInstructionAccessMMUMiss(req->getVaddr());
+#endif
     }
 
     // were not priviledged accesing priv page
@@ -744,7 +748,11 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
         if (real)
             return new DataRealTranslationMiss;
         else
+#if FULL_SYSTEM
             return new FastDataAccessMMUMiss;
+#else
+            return new FastDataAccessMMUMiss(req->getVaddr());
+#endif
 
     }
 
@@ -853,6 +861,8 @@ handleMmuRegAccess:
     return NoFault;
 };
 
+#if FULL_SYSTEM
+
 Tick
 DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 {
@@ -1275,6 +1285,8 @@ doMmuWriteError:
     return tc->getCpuPtr()->cycles(1);
 }
 
+#endif
+
 void
 DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
 {
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index e1111db8d..d35a6e096 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -34,6 +34,7 @@
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/tlb_map.hh"
 #include "base/misc.hh"
+#include "config/full_system.hh"
 #include "mem/request.hh"
 #include "sim/faults.hh"
 #include "sim/sim_object.hh"
@@ -46,6 +47,12 @@ namespace SparcISA
 
 class TLB : public SimObject
 {
+#if !FULL_SYSTEM
+    //These faults need to be able to populate the tlb in SE mode.
+    friend class FastInstructionAccessMMUMiss;
+    friend class FastDataAccessMMUMiss;
+#endif
+
     //TLB state
   protected:
     uint64_t c0_tsb_ps0;
@@ -183,8 +190,10 @@ class DTB : public TLB
     }
 
     Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+#if FULL_SYSTEM
     Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
+#endif
     void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
 
     // Checkpointing