diff options
author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-13 00:05:52 -0400 |
---|---|---|
committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-13 00:05:52 -0400 |
commit | a068d6db0fff7056abb06bb8a99494b63bd169e1 (patch) | |
tree | e52f43a1cbbc6a6ea36ffe0d457a6d4b30fbf5f6 /src/arch/sparc | |
parent | 247ee8ef743f46418ca846def20be1cc3a3ade18 (diff) | |
download | gem5-a068d6db0fff7056abb06bb8a99494b63bd169e1.tar.xz |
fix interrupting during a quisce on sparc
src/arch/sparc/ua2005.cc:
fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to
check if were suspended and interrupt at the guess time
src/base/traceflags.py:
add trace flag for Iob
src/cpu/simple/base.cc:
Use Quisce instead of IPI trace flag
src/dev/sparc/iob.cc:
add some Dprintfs
--HG--
extra : convert_revision : 72e18fcc750ad1e4b2bb67b19b354eaffc6af6d5
Diffstat (limited to 'src/arch/sparc')
-rw-r--r-- | src/arch/sparc/ua2005.cc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 865280038..48e97a531 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -195,6 +195,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) panic("No support for setting spec_en bit\n"); setRegNoEffect(miscReg, bits(val,0,0)); if (!bits(val,0,0)) { + DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); // Time to go to sleep tc->suspend(); if (tc->getKernelStats()) @@ -307,7 +308,7 @@ MiscRegFile::processSTickCompare(ThreadContext *tc) tc->getCpuPtr()->instCount(); assert(ticks >= 0 && "stick compare missed interrupt cycle"); - if (ticks == 0) { + if (ticks == 0 || tc->status() == ThreadContext::Suspended) { DPRINTF(Timer, "STick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { @@ -324,11 +325,15 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc) // we're actually at the correct cycle or we need to wait a little while // more int ticks; + if ( tc->status() == ThreadContext::Halted || + tc->status() == ThreadContext::Unallocated) + return; + ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - tc->getCpuPtr()->instCount(); assert(ticks >= 0 && "hstick compare missed interrupt cycle"); - if (ticks == 0) { + if (ticks == 0 || tc->status() == ThreadContext::Suspended) { DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", (stick_cmpr & mask(63))); if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { |