Merge zizzer.eecs.umich.edu:/bk/newmem

into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem

--HG--
extra : convert_revision : d764fe37c71269a04fcede6cbf30e24262447e89

15 files changed, 363 insertions, 363 deletions

diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index b1a6ae919..f6cf97872 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -282,17 +282,17 @@ void enterREDState(ThreadContext *tc)
 {
     //@todo Disable the mmu?
     //@todo Disable watchpoints?
-    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
+    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
     //HPSTATE.red = 1
     HPSTATE |= (1 << 5);
     //HPSTATE.hpriv = 1
     HPSTATE |= (1 << 2);
-    tc->setMiscRegWithEffect(MISCREG_HPSTATE, HPSTATE);
+    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
     //PSTATE.priv is set to 1 here. The manual says it should be 0, but
     //Legion sets it to 1.
-    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
+    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
     PSTATE |= (1 << 2);
-    tc->setMiscRegWithEffect(MISCREG_PSTATE, PSTATE);
+    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
 }
 
 /**
@@ -302,17 +302,17 @@ void enterREDState(ThreadContext *tc)
 
 void doREDFault(ThreadContext *tc, TrapType tt)
 {
-    MiscReg TL = tc->readMiscReg(MISCREG_TL);
-    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
-    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
-    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
-    //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
+    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
+    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
+    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
+    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
+    //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
     MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
-    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
-    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
-    //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
-    MiscReg CANSAVE = tc->readMiscReg(NumIntArchRegs + 3);
-    MiscReg GL = tc->readMiscReg(MISCREG_GL);
+    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
+    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
+    //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
+    MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
+    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
     MiscReg PC = tc->readPC();
     MiscReg NPC = tc->readNextPC();
 
@@ -335,25 +335,25 @@ void doREDFault(ThreadContext *tc, TrapType tt)
     replaceBits(TSTATE, 4, 0, CWP);
 
     //Write back TSTATE
-    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
+    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
 
     //set TPC to PC
-    tc->setMiscReg(MISCREG_TPC, PC);
+    tc->setMiscRegNoEffect(MISCREG_TPC, PC);
     //set TNPC to NPC
-    tc->setMiscReg(MISCREG_TNPC, NPC);
+    tc->setMiscRegNoEffect(MISCREG_TNPC, NPC);
 
     //set HTSTATE.hpstate to hpstate
-    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
+    tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
 
     //TT = trap type;
-    tc->setMiscReg(MISCREG_TT, tt);
+    tc->setMiscRegNoEffect(MISCREG_TT, tt);
 
     //Update GL
-    tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
+    tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
 
     PSTATE = mbits(PSTATE, 2, 2); // just save the priv bit
     PSTATE |= (1 << 4); //set PSTATE.pef to 1
-    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
+    tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
 
     //set HPSTATE.red to 1
     HPSTATE |= (1 << 5);
@@ -363,7 +363,7 @@ void doREDFault(ThreadContext *tc, TrapType tt)
     HPSTATE &= ~(1 << 10);
     //set HPSTATE.tlz to 0
     HPSTATE &= ~(1 << 0);
-    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
+    tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
 
     bool changedCWP = true;
     if(tt == 0x24)
@@ -378,7 +378,7 @@ void doREDFault(ThreadContext *tc, TrapType tt)
     if(changedCWP)
     {
         CWP = (CWP + NWindows) % NWindows;
-        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
+        tc->setMiscReg(MISCREG_CWP, CWP);
     }
 }
 
@@ -389,17 +389,17 @@ void doREDFault(ThreadContext *tc, TrapType tt)
 
 void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
 {
-    MiscReg TL = tc->readMiscReg(MISCREG_TL);
-    MiscReg TSTATE = tc->readMiscReg(MISCREG_TSTATE);
-    MiscReg PSTATE = tc->readMiscReg(MISCREG_PSTATE);
-    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
-    //MiscReg CCR = tc->readMiscReg(MISCREG_CCR);
+    MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
+    MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
+    MiscReg PSTATE = tc->readMiscRegNoEffect(MISCREG_PSTATE);
+    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
+    //MiscReg CCR = tc->readMiscRegNoEffect(MISCREG_CCR);
     MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
-    MiscReg ASI = tc->readMiscReg(MISCREG_ASI);
-    MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
-    //MiscReg CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
+    MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
+    MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
+    //MiscReg CANSAVE = tc->readMiscRegNoEffect(MISCREG_CANSAVE);
     MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
-    MiscReg GL = tc->readMiscReg(MISCREG_GL);
+    MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
     MiscReg PC = tc->readPC();
     MiscReg NPC = tc->readNextPC();
 
@@ -410,7 +410,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
 
     //Increment the trap level
     TL++;
-    tc->setMiscReg(MISCREG_TL, TL);
+    tc->setMiscRegNoEffect(MISCREG_TL, TL);
 
     //Save off state
 
@@ -426,24 +426,24 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
     replaceBits(TSTATE, 4, 0, CWP);
 
     //Write back TSTATE
-    tc->setMiscReg(MISCREG_TSTATE, TSTATE);
+    tc->setMiscRegNoEffect(MISCREG_TSTATE, TSTATE);
 
     //set TPC to PC
-    tc->setMiscReg(MISCREG_TPC, PC);
+    tc->setMiscRegNoEffect(MISCREG_TPC, PC);
     //set TNPC to NPC
-    tc->setMiscReg(MISCREG_TNPC, NPC);
+    tc->setMiscRegNoEffect(MISCREG_TNPC, NPC);
 
     //set HTSTATE.hpstate to hpstate
-    tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
+    tc->setMiscRegNoEffect(MISCREG_HTSTATE, HPSTATE);
 
     //TT = trap type;
-    tc->setMiscReg(MISCREG_TT, tt);
+    tc->setMiscRegNoEffect(MISCREG_TT, tt);
 
     //Update the global register level
     if (!gotoHpriv)
-        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxPGL));
+        tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxPGL));
     else
-        tc->setMiscRegWithEffect(MISCREG_GL, min<int>(GL+1, MaxGL));
+        tc->setMiscReg(MISCREG_GL, min<int>(GL+1, MaxGL));
 
     //PSTATE.mm is unchanged
     PSTATE |= (1 << 4); //PSTATE.pef = whether or not an fpu is present
@@ -460,12 +460,12 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
         HPSTATE |= (1 << 2); //HPSTATE.hpriv = 1
         HPSTATE &= ~(1 << 10); //HPSTATE.ibe = 0
         //HPSTATE.tlz is unchanged
-        tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
+        tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
     } else { // we are going to priv
         PSTATE |= (1 << 2); //PSTATE.priv = 1
         replaceBits(PSTATE, 9, 9, PSTATE >> 8); //PSTATE.cle = PSTATE.tle
     }
-    tc->setMiscReg(MISCREG_PSTATE, PSTATE);
+    tc->setMiscRegNoEffect(MISCREG_PSTATE, PSTATE);
 
 
     bool changedCWP = true;
@@ -481,7 +481,7 @@ void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
     if (changedCWP)
     {
         CWP = (CWP + NWindows) % NWindows;
-        tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
+        tc->setMiscReg(MISCREG_CWP, CWP);
     }
 }
 
@@ -495,14 +495,14 @@ void getREDVector(MiscReg TT, Addr & PC, Addr & NPC)
 
 void getHyperVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT)
 {
-    Addr HTBA = tc->readMiscReg(MISCREG_HTBA);
+    Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
     PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
     NPC = PC + sizeof(MachInst);
 }
 
 void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscReg TL)
 {
-    Addr TBA = tc->readMiscReg(MISCREG_TBA);
+    Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
     PC = (TBA & ~mask(15)) |
         (TL > 1 ? (1 << 14) : 0) |
         ((TT << 5) & mask(14));
@@ -519,10 +519,10 @@ void SparcFaultBase::invoke(ThreadContext * tc)
 
     //We can refer to this to see what the trap level -was-, but something
     //in the middle could change it in the regfile out from under us.
-    MiscReg tl = tc->readMiscReg(MISCREG_TL);
-    MiscReg tt = tc->readMiscReg(MISCREG_TT);
-    MiscReg pstate = tc->readMiscReg(MISCREG_PSTATE);
-    MiscReg hpstate = tc->readMiscReg(MISCREG_HPSTATE);
+    MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
+    MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
+    MiscReg pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
+    MiscReg hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
 
     Addr PC, NPC;
 
@@ -571,15 +571,15 @@ void PowerOnReset::invoke(ThreadContext * tc)
     //on reset Trap which sets the processor into the following state.
     //Bits that aren't set aren't defined on startup.
 
-    tc->setMiscReg(MISCREG_TL, MaxTL);
-    tc->setMiscReg(MISCREG_TT, trapType());
-    tc->setMiscRegWithEffect(MISCREG_GL, MaxGL);
+    tc->setMiscRegNoEffect(MISCREG_TL, MaxTL);
+    tc->setMiscRegNoEffect(MISCREG_TT, trapType());
+    tc->setMiscReg(MISCREG_GL, MaxGL);
 
     //Turn on pef and priv, set everything else to 0
-    tc->setMiscReg(MISCREG_PSTATE, (1 << 4) | (1 << 2));
+    tc->setMiscRegNoEffect(MISCREG_PSTATE, (1 << 4) | (1 << 2));
 
     //Turn on red and hpriv, set everything else to 0
-    MiscReg HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
+    MiscReg HPSTATE = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
     //HPSTATE.red = 1
     HPSTATE |= (1 << 5);
     //HPSTATE.hpriv = 1
@@ -588,10 +588,10 @@ void PowerOnReset::invoke(ThreadContext * tc)
     HPSTATE &= ~(1 << 10);
     //HPSTATE.tlz = 0
     HPSTATE &= ~(1 << 0);
-    tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
+    tc->setMiscRegNoEffect(MISCREG_HPSTATE, HPSTATE);
 
     //The tick register is unreadable by nonprivileged software
-    tc->setMiscReg(MISCREG_TICK, 1ULL << 63);
+    tc->setMiscRegNoEffect(MISCREG_TICK, 1ULL << 63);
 
     //Enter RED state. We do this last so that the actual state preserved in
     //the trap stack is the state from before this fault.
@@ -609,7 +609,7 @@ void PowerOnReset::invoke(ThreadContext * tc)
     // Clear all the soft interrupt bits
     softint = 0;
     // disable timer compare interrupts, reset tick_cmpr
-    tc->setMiscReg(MISCREG_
+    tc->setMiscRegNoEffect(MISCREG_
     tick_cmprFields.int_dis = 1;
     tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
     stickFields.npt = 1; //The TICK register is unreadable by by !priv
diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
index 3234002c5..4ad3385fb 100644
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/sparc/interrupts.hh
@@ -102,8 +102,8 @@ class Interrupts
 
     Fault getInterrupt(ThreadContext * tc)
     {
-        int hpstate = tc->readMiscReg(MISCREG_HPSTATE);
-        int pstate = tc->readMiscReg(MISCREG_PSTATE);
+        int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
+        int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
         bool ie = pstate & PSTATE::ie;
 
         // THESE ARE IN ORDER OF PRIORITY
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 693cc6876..bba63f407 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -492,8 +492,8 @@ output exec {{
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault;	// dummy... this ipr access should not fault
-        if (xc->readMiscRegWithEffect(MISCREG_PSTATE) & PSTATE::pef &&
-            xc->readMiscRegWithEffect(MISCREG_FPRS) & 0x4)
+        if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
+            xc->readMiscReg(MISCREG_FPRS) & 0x4)
             return NoFault;
         else
             return new FpDisabled;
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index 849eed1cc..e7b866e6f 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -140,7 +140,7 @@ void MiscRegFile::clear()
 #endif
 }
 
-MiscReg MiscRegFile::readReg(int miscReg)
+MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 {
     switch (miscReg) {
       case MISCREG_TLB_DATA:
@@ -331,7 +331,7 @@ MiscReg MiscRegFile::readReg(int miscReg)
     }
 }
 
-MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
+MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
 {
     switch (miscReg) {
         // tick and stick are aliased to each other in niagra
@@ -386,10 +386,10 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
 #endif
 
     }
-    return readReg(miscReg);
+    return readRegNoEffect(miscReg);
 }
 
-void MiscRegFile::setReg(int miscReg, const MiscReg &val)
+void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
 {
     switch (miscReg) {
 //      case MISCREG_Y:
@@ -621,7 +621,7 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
     }
 }
 
-void MiscRegFile::setRegWithEffect(int miscReg,
+void MiscRegFile::setReg(int miscReg,
         const MiscReg &val, ThreadContext * tc)
 {
     MiscReg new_val = val;
@@ -692,7 +692,7 @@ void MiscRegFile::setRegWithEffect(int miscReg,
       panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
 #endif
     }
-    setReg(miscReg, new_val);
+    setRegNoEffect(miscReg, new_val);
 }
 
 void MiscRegFile::serialize(std::ostream & os)
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index ac0e930c5..cb46eb2aa 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -291,13 +291,13 @@ namespace SparcISA
             clear();
         }
 
-        MiscReg readReg(int miscReg);
+        MiscReg readRegNoEffect(int miscReg);
 
-        MiscReg readRegWithEffect(int miscReg, ThreadContext *tc);
+        MiscReg readReg(int miscReg, ThreadContext *tc);
 
-        void setReg(int miscReg, const MiscReg &val);
+        void setRegNoEffect(int miscReg, const MiscReg &val);
 
-        void setRegWithEffect(int miscReg,
+        void setReg(int miscReg,
                 const MiscReg &val, ThreadContext * tc);
 
         int getInstAsid()
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index c3b833562..a6cefa080 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -88,38 +88,38 @@ Sparc32LiveProcess::startup()
     //From the SPARC ABI
 
     //The process runs in user mode
-    threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02);
+    threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x02);
 
     //Setup default FP state
-    threadContexts[0]->setMiscReg(MISCREG_FSR, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0);
 
-    threadContexts[0]->setMiscReg(MISCREG_TICK, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0);
     //
     /*
      * Register window management registers
      */
 
     //No windows contain info from other programs
-    //threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
     threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0);
     //There are no windows to pop
-    //threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANRESTORE, 0);
     threadContexts[0]->setIntReg(NumIntArchRegs + 4, 0);
     //All windows are available to save into
-    //threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2);
     threadContexts[0]->setIntReg(NumIntArchRegs + 3, NWindows - 2);
     //All windows are "clean"
-    //threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows);
     threadContexts[0]->setIntReg(NumIntArchRegs + 5, NWindows);
     //Start with register window 0
-    threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_CWP, 0);
     //Always use spill and fill traps 0
-    //threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_WSTATE, 0);
     threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0);
     //Set the trap level to 0
-    threadContexts[0]->setMiscReg(MISCREG_TL, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
     //Set the ASI register to something fixed
-    threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
 }
 
 void
@@ -130,38 +130,38 @@ Sparc64LiveProcess::startup()
     //From the SPARC ABI
 
     //The process runs in user mode
-    threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02);
+    threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x02);
 
     //Setup default FP state
-    threadContexts[0]->setMiscReg(MISCREG_FSR, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0);
 
-    threadContexts[0]->setMiscReg(MISCREG_TICK, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0);
     //
     /*
      * Register window management registers
      */
 
     //No windows contain info from other programs
-    //threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
     threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0);
     //There are no windows to pop
-    //threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANRESTORE, 0);
     threadContexts[0]->setIntReg(NumIntArchRegs + 4, 0);
     //All windows are available to save into
-    //threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2);
     threadContexts[0]->setIntReg(NumIntArchRegs + 3, NWindows - 2);
     //All windows are "clean"
-    //threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows);
     threadContexts[0]->setIntReg(NumIntArchRegs + 5, NWindows);
     //Start with register window 0
-    threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_CWP, 0);
     //Always use spill and fill traps 0
-    //threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
+    //threadContexts[0]->setMiscRegNoEffect(MISCREG_WSTATE, 0);
     threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0);
     //Set the trap level to 0
-    threadContexts[0]->setMiscReg(MISCREG_TL, 0);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
     //Set the ASI register to something fixed
-    threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
+    threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
 }
 
 M5_32_auxv_t::M5_32_auxv_t(int32_t type, int32_t val)
diff --git a/src/arch/sparc/regfile.cc b/src/arch/sparc/regfile.cc
index 944b1f401..667b1f002 100644
--- a/src/arch/sparc/regfile.cc
+++ b/src/arch/sparc/regfile.cc
@@ -75,25 +75,25 @@ void RegFile::clear()
     miscRegFile.clear();
 }
 
-MiscReg RegFile::readMiscReg(int miscReg)
+MiscReg RegFile::readMiscRegNoEffect(int miscReg)
 {
-    return miscRegFile.readReg(miscReg);
+    return miscRegFile.readRegNoEffect(miscReg);
 }
 
-MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc)
+MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
 {
-    return miscRegFile.readRegWithEffect(miscReg, tc);
+    return miscRegFile.readReg(miscReg, tc);
 }
 
-void RegFile::setMiscReg(int miscReg, const MiscReg &val)
+void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
 {
-    miscRegFile.setReg(miscReg, val);
+    miscRegFile.setRegNoEffect(miscReg, val);
 }
 
-void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
+void RegFile::setMiscReg(int miscReg, const MiscReg &val,
         ThreadContext * tc)
 {
-    miscRegFile.setRegWithEffect(miscReg, val, tc);
+    miscRegFile.setReg(miscReg, val, tc);
 }
 
 FloatReg RegFile::readFloatReg(int floatReg, int width)
@@ -153,8 +153,8 @@ void RegFile::setIntReg(int intReg, const IntReg &val)
 
 int SparcISA::flattenIntIndex(ThreadContext * tc, int reg)
 {
-    int gl = tc->readMiscReg(MISCREG_GL);
-    int cwp = tc->readMiscReg(MISCREG_CWP);
+    int gl = tc->readMiscRegNoEffect(MISCREG_GL);
+    int cwp = tc->readMiscRegNoEffect(MISCREG_CWP);
     //DPRINTF(Sparc, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
     int newReg;
     //The total number of global registers
@@ -257,146 +257,146 @@ void RegFile::changeContext(RegContextParam param, RegContextVal val)
 void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 {
 
-    uint8_t tl = src->readMiscReg(MISCREG_TL);
+    uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
 
     // Read all the trap level dependent registers and save them off
     for(int i = 1; i <= MaxTL; i++)
     {
-        src->setMiscReg(MISCREG_TL, i);
-        dest->setMiscReg(MISCREG_TL, i);
+        src->setMiscRegNoEffect(MISCREG_TL, i);
+        dest->setMiscRegNoEffect(MISCREG_TL, i);
 
-        dest->setMiscReg(MISCREG_TT, src->readMiscReg(MISCREG_TT));
-        dest->setMiscReg(MISCREG_TPC, src->readMiscReg(MISCREG_TPC));
-        dest->setMiscReg(MISCREG_TNPC, src->readMiscReg(MISCREG_TNPC));
-        dest->setMiscReg(MISCREG_TSTATE, src->readMiscReg(MISCREG_TSTATE));
+        dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT));
+        dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC));
+        dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC));
+        dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE));
     }
 
     // Save off the traplevel
-    dest->setMiscReg(MISCREG_TL, tl);
-    src->setMiscReg(MISCREG_TL, tl);
+    dest->setMiscRegNoEffect(MISCREG_TL, tl);
+    src->setMiscRegNoEffect(MISCREG_TL, tl);
 
 
     // ASRs
-//    dest->setMiscReg(MISCREG_Y, src->readMiscReg(MISCREG_Y));
-//    dest->setMiscReg(MISCREG_CCR, src->readMiscReg(MISCREG_CCR));
-    dest->setMiscReg(MISCREG_ASI, src->readMiscReg(MISCREG_ASI));
-    dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK));
-    dest->setMiscReg(MISCREG_FPRS, src->readMiscReg(MISCREG_FPRS));
-    dest->setMiscReg(MISCREG_SOFTINT, src->readMiscReg(MISCREG_SOFTINT));
-    dest->setMiscReg(MISCREG_TICK_CMPR, src->readMiscReg(MISCREG_TICK_CMPR));
-    dest->setMiscReg(MISCREG_STICK, src->readMiscReg(MISCREG_STICK));
-    dest->setMiscReg(MISCREG_STICK_CMPR, src->readMiscReg(MISCREG_STICK_CMPR));
+//    dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y));
+//    dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR));
+    dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI));
+    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
+    dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS));
+    dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT));
+    dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
+    dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK));
+    dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
 
     // Priv Registers
-    dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK));
-    dest->setMiscReg(MISCREG_TBA, src->readMiscReg(MISCREG_TBA));
-    dest->setMiscReg(MISCREG_PSTATE, src->readMiscReg(MISCREG_PSTATE));
-    dest->setMiscReg(MISCREG_PIL, src->readMiscReg(MISCREG_PIL));
-    dest->setMiscReg(MISCREG_CWP, src->readMiscReg(MISCREG_CWP));
-//    dest->setMiscReg(MISCREG_CANSAVE, src->readMiscReg(MISCREG_CANSAVE));
-//    dest->setMiscReg(MISCREG_CANRESTORE, src->readMiscReg(MISCREG_CANRESTORE));
-//    dest->setMiscReg(MISCREG_OTHERWIN, src->readMiscReg(MISCREG_OTHERWIN));
-//    dest->setMiscReg(MISCREG_CLEANWIN, src->readMiscReg(MISCREG_CLEANWIN));
-//    dest->setMiscReg(MISCREG_WSTATE, src->readMiscReg(MISCREG_WSTATE));
-    dest->setMiscReg(MISCREG_GL, src->readMiscReg(MISCREG_GL));
+    dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
+    dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA));
+    dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE));
+    dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL));
+    dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP));
+//    dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE));
+//    dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE));
+//    dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN));
+//    dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN));
+//    dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE));
+    dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
 
     // Hyperprivilged registers
-    dest->setMiscReg(MISCREG_HPSTATE, src->readMiscReg(MISCREG_HPSTATE));
-    dest->setMiscReg(MISCREG_HINTP, src->readMiscReg(MISCREG_HINTP));
-    dest->setMiscReg(MISCREG_HTBA, src->readMiscReg(MISCREG_HTBA));
-    dest->setMiscReg(MISCREG_STRAND_STS_REG,
-            src->readMiscReg(MISCREG_STRAND_STS_REG));
-    dest->setMiscReg(MISCREG_HSTICK_CMPR,
-            src->readMiscReg(MISCREG_HSTICK_CMPR));
+    dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE));
+    dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP));
+    dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA));
+    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
+            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
+    dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
+            src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
 
     // FSR
-    dest->setMiscReg(MISCREG_FSR, src->readMiscReg(MISCREG_FSR));
+    dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR));
 
     //Strand Status Register
-    dest->setMiscReg(MISCREG_STRAND_STS_REG,
-            src->readMiscReg(MISCREG_STRAND_STS_REG));
+    dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
+            src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
 
     // MMU Registers
-    dest->setMiscReg(MISCREG_MMU_P_CONTEXT,
-            src->readMiscReg(MISCREG_MMU_P_CONTEXT));
-    dest->setMiscReg(MISCREG_MMU_S_CONTEXT,
-            src->readMiscReg(MISCREG_MMU_S_CONTEXT));
-    dest->setMiscReg(MISCREG_MMU_PART_ID,
-            src->readMiscReg(MISCREG_MMU_PART_ID));
-    dest->setMiscReg(MISCREG_MMU_LSU_CTRL,
-            src->readMiscReg(MISCREG_MMU_LSU_CTRL));
-
-    dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0,
-            src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0));
-    dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1,
-            src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1));
-    dest->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG,
-            src->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG));
-    dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0,
-            src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0));
-    dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1,
-            src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1));
-    dest->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG,
-            src->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
-    dest->setMiscReg(MISCREG_MMU_ITLB_SFSR,
-            src->readMiscReg(MISCREG_MMU_ITLB_SFSR));
-    dest->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS,
-            src->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS));
-
-    dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0,
-            src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0));
-    dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1,
-            src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1));
-    dest->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG,
-            src->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG));
-    dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0,
-            src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0));
-    dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1,
-            src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1));
-    dest->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG,
-            src->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
-    dest->setMiscReg(MISCREG_MMU_DTLB_SFSR,
-            src->readMiscReg(MISCREG_MMU_DTLB_SFSR));
-    dest->setMiscReg(MISCREG_MMU_DTLB_SFAR,
-            src->readMiscReg(MISCREG_MMU_DTLB_SFAR));
-    dest->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
-            src->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS));
+    dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
+            src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
+    dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
+            src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
+    dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
+            src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
+    dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
+            src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
+
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_C0_TSB_PS0,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_C0_TSB_PS1,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_C0_CONFIG,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_C0_CONFIG));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_CX_TSB_PS0,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_CX_TSB_PS1,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_CX_CONFIG,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_CX_CONFIG));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_SFSR,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_SFSR));
+    dest->setMiscRegNoEffect(MISCREG_MMU_ITLB_TAG_ACCESS,
+            src->readMiscRegNoEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
+
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_C0_TSB_PS0,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_C0_TSB_PS1,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_C0_CONFIG,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_C0_CONFIG));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_CX_TSB_PS0,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_CX_TSB_PS1,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_CX_CONFIG,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_CX_CONFIG));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_SFSR,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_SFSR));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_SFAR,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_SFAR));
+    dest->setMiscRegNoEffect(MISCREG_MMU_DTLB_TAG_ACCESS,
+            src->readMiscRegNoEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
 
     // Scratchpad Registers
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R0,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R0));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R1,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R1));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R2,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R2));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R3,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R3));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R4,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R4));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R5,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R5));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R6,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R6));
-    dest->setMiscReg(MISCREG_SCRATCHPAD_R7,
-            src->readMiscReg(MISCREG_SCRATCHPAD_R7));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
+    dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
+            src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
 
     // Queue Registers
-    dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD,
-            src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD));
-    dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL,
-            src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL));
-    dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD,
-            src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD));
-    dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL,
-            src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL));
-    dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD,
-            src->readMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD));
-    dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL,
-            src->readMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL));
-    dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD,
-            src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD));
-    dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL,
-            src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
+    dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
+            src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
 }
 
 void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest)
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index 9e0b3beb3..f3e253f7e 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -73,13 +73,13 @@ namespace SparcISA
 
         int FlattenIntIndex(int reg);
 
-        MiscReg readMiscReg(int miscReg);
+        MiscReg readMiscRegNoEffect(int miscReg);
 
-        MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc);
+        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
 
-        void setMiscReg(int miscReg, const MiscReg &val);
+        void setMiscRegNoEffect(int miscReg, const MiscReg &val);
 
-        void setMiscRegWithEffect(int miscReg, const MiscReg &val,
+        void setMiscReg(int miscReg, const MiscReg &val,
                 ThreadContext * tc);
 
         int instAsid()
diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
index e2ea7a84d..85b0c03a3 100644
--- a/src/arch/sparc/remote_gdb.cc
+++ b/src/arch/sparc/remote_gdb.cc
@@ -167,7 +167,7 @@ RemoteGDB::getregs()
 {
     memset(gdbregs.regs, 0, gdbregs.size);
 
-    if (context->readMiscRegWithEffect(MISCREG_PSTATE) &
+    if (context->readMiscReg(MISCREG_PSTATE) &
            PSTATE::am) {
         uint32_t *regs;
         regs = (uint32_t*)gdbregs.regs;
@@ -177,8 +177,8 @@ RemoteGDB::getregs()
             regs[x] = htobe((uint32_t)context->readIntReg(x - RegG0));
 
         regs[Reg32Y] = htobe((uint32_t)context->readIntReg(NumIntArchRegs + 1));
-        regs[Reg32Psr] = htobe((uint32_t)context->readMiscRegWithEffect(MISCREG_PSTATE));
-        regs[Reg32Fsr] = htobe((uint32_t)context->readMiscRegWithEffect(MISCREG_FSR));
+        regs[Reg32Psr] = htobe((uint32_t)context->readMiscReg(MISCREG_PSTATE));
+        regs[Reg32Fsr] = htobe((uint32_t)context->readMiscReg(MISCREG_FSR));
         regs[Reg32Csr] = htobe((uint32_t)context->readIntReg(NumIntArchRegs + 2));
     } else {
         gdbregs.regs[RegPc] = htobe(context->readPC());
@@ -186,13 +186,13 @@ RemoteGDB::getregs()
         for(int x = RegG0; x <= RegI0 + 7; x++)
             gdbregs.regs[x] = htobe(context->readIntReg(x - RegG0));
 
-        gdbregs.regs[RegFsr] = htobe(context->readMiscRegWithEffect(MISCREG_FSR));
-        gdbregs.regs[RegFprs] = htobe(context->readMiscRegWithEffect(MISCREG_FPRS));
+        gdbregs.regs[RegFsr] = htobe(context->readMiscReg(MISCREG_FSR));
+        gdbregs.regs[RegFprs] = htobe(context->readMiscReg(MISCREG_FPRS));
         gdbregs.regs[RegY] = htobe(context->readIntReg(NumIntArchRegs + 1));
         gdbregs.regs[RegState] = htobe(
-            context->readMiscRegWithEffect(MISCREG_CWP) |
-            context->readMiscRegWithEffect(MISCREG_PSTATE) << 8 |
-            context->readMiscRegWithEffect(MISCREG_ASI) << 24 |
+            context->readMiscReg(MISCREG_CWP) |
+            context->readMiscReg(MISCREG_PSTATE) << 8 |
+            context->readMiscReg(MISCREG_ASI) << 24 |
             context->readIntReg(NumIntArchRegs + 2) << 32);
     }
 
diff --git a/src/arch/sparc/stacktrace.cc b/src/arch/sparc/stacktrace.cc
index 2eb697bf2..2d7991267 100644
--- a/src/arch/sparc/stacktrace.cc
+++ b/src/arch/sparc/stacktrace.cc
@@ -146,7 +146,7 @@ namespace SparcISA
 #if 0
         tc = _tc;
 
-        bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+        bool usermode = (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
 
         Addr pc = tc->readNextPC();
         bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
@@ -221,22 +221,22 @@ namespace SparcISA
     StackTrace::isEntry(Addr addr)
     {
 #if 0
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp12))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp7))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp11))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp21))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp9))
             return true;
 
-        if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2))
+        if (addr == tc->readMiscRegNoEffect(AlphaISA::IPR_PALtemp2))
             return true;
 #endif
         return false;
diff --git a/src/arch/sparc/syscallreturn.hh b/src/arch/sparc/syscallreturn.hh
index d92b12790..cf13fc3e8 100644
--- a/src/arch/sparc/syscallreturn.hh
+++ b/src/arch/sparc/syscallreturn.hh
@@ -49,13 +49,13 @@ namespace SparcISA
             // no error, clear XCC.C
             tc->setIntReg(NumIntArchRegs + 2,
                     tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
-            //tc->setMiscReg(MISCREG_CCR, tc->readMiscReg(MISCREG_CCR) & 0xEE);
+            //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE);
             tc->setIntReg(ReturnValueReg, return_value.value());
         } else {
             // got an error, set XCC.C
             tc->setIntReg(NumIntArchRegs + 2,
                     tc->readIntReg(NumIntArchRegs + 2) | 0x11);
-            //tc->setMiscReg(MISCREG_CCR, tc->readMiscReg(MISCREG_CCR) | 0x11);
+            //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11);
             tc->setIntReg(ReturnValueReg, -return_value.value());
         }
     }
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 41d55158e..c39969769 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -396,7 +396,7 @@ TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
         bool se, FaultTypes ft, int asi)
 {
     uint64_t sfsr;
-    sfsr = tc->readMiscReg(reg);
+    sfsr = tc->readMiscRegNoEffect(reg);
 
     if (sfsr & 0x1)
         sfsr = 0x3;
@@ -410,7 +410,7 @@ TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
         sfsr |= 1 << 6;
     sfsr |= ft << 7;
     sfsr |= asi << 16;
-    tc->setMiscRegWithEffect(reg, sfsr);
+    tc->setMiscReg(reg, sfsr);
 }
 
 void
@@ -419,7 +419,7 @@ TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
     DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
             va, context, mbits(va, 63,13) | mbits(context,12,0));
 
-    tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
+    tc->setMiscReg(reg, mbits(va, 63,13) | mbits(context,12,0));
 }
 
 void
@@ -444,7 +444,7 @@ DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
     DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
             a, (int)write, ct, ft, asi);
     TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
-    tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
+    tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a);
 }
 
 void
@@ -458,7 +458,7 @@ DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
 Fault
 ITB::translate(RequestPtr &req, ThreadContext *tc)
 {
-    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
+    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
 
     Addr vaddr = req->getVaddr();
     TlbEntry *e;
@@ -572,7 +572,7 @@ Fault
 DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 {
     /* @todo this could really use some profiling and fixing to make it faster! */
-    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
+    uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
     Addr vaddr = req->getVaddr();
     Addr size = req->getSize();
     ASI asi;
@@ -864,90 +864,90 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
     switch (asi) {
       case ASI_LSU_CONTROL_REG:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
         break;
       case ASI_MMU:
         switch (va) {
           case 0x8:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
             break;
           case 0x10:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
             break;
           default:
             goto doMmuReadError;
         }
         break;
       case ASI_QUEUE:
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
+        pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
                     (va >> 4) - 0x3c));
         break;
       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0));
         break;
       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1));
         break;
       case ASI_DMMU_CTXT_ZERO_CONFIG:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG));
         break;
       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0));
         break;
       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1));
         break;
       case ASI_IMMU_CTXT_ZERO_CONFIG:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG));
         break;
       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0));
         break;
       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1));
         break;
       case ASI_DMMU_CTXT_NONZERO_CONFIG:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
         break;
       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0));
         break;
       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1));
         break;
       case ASI_IMMU_CTXT_NONZERO_CONFIG:
         assert(va == 0);
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
+        pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
         break;
       case ASI_SPARC_ERROR_STATUS_REG:
         pkt->set((uint64_t)0);
         break;
       case ASI_HYP_SCRATCHPAD:
       case ASI_SCRATCHPAD:
-        pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
+        pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
         break;
       case ASI_IMMU:
         switch (va) {
           case 0x0:
-            temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
+            temp = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS);
             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
             break;
           case 0x18:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_SFSR));
             break;
           case 0x30:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS));
             break;
           default:
             goto doMmuReadError;
@@ -956,20 +956,20 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
       case ASI_DMMU:
         switch (va) {
           case 0x0:
-            temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
+            temp = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS);
             pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
             break;
           case 0x18:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFSR));
             break;
           case 0x20:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFAR));
             break;
           case 0x30:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS));
             break;
           case 0x80:
-            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
+            pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
             break;
           default:
                 goto doMmuReadError;
@@ -977,35 +977,35 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
         break;
       case ASI_DMMU_TSB_PS0_PTR_REG:
         pkt->set(MakeTsbPtr(Ps0,
-            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS),
-            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0),
-            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
-            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0),
-            tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)));
+            tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS),
+            tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0),
+            tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
+            tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0),
+            tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)));
         break;
       case ASI_DMMU_TSB_PS1_PTR_REG:
         pkt->set(MakeTsbPtr(Ps1,
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)));
+                tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS),
+                tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)));
         break;
       case ASI_IMMU_TSB_PS0_PTR_REG:
           pkt->set(MakeTsbPtr(Ps0,
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)));
+                tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS),
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0),
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)));
         break;
       case ASI_IMMU_TSB_PS1_PTR_REG:
           pkt->set(MakeTsbPtr(Ps1,
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)));
+                tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS),
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)));
         break;
       case ASI_SWVR_INTR_RECEIVE:
         pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
@@ -1048,15 +1048,15 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
     switch (asi) {
       case ASI_LSU_CONTROL_REG:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
+        tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
         break;
       case ASI_MMU:
         switch (va) {
           case 0x8:
-            tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
+            tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
             break;
           case 0x10:
-            tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
+            tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
             break;
           default:
             goto doMmuWriteError;
@@ -1064,56 +1064,56 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
         break;
       case ASI_QUEUE:
         assert(mbits(data,13,6) == data);
-        tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
+        tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
                     (va >> 4) - 0x3c, data);
         break;
       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
+        tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
         break;
       case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
+        tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
         break;
       case ASI_DMMU_CTXT_ZERO_CONFIG:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
+        tc->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG, data);
         break;
       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
+        tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
         break;
       case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
+        tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
         break;
       case ASI_IMMU_CTXT_ZERO_CONFIG:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
+        tc->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG, data);
         break;
       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
+        tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
         break;
       case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
+        tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
         break;
       case ASI_DMMU_CTXT_NONZERO_CONFIG:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
+        tc->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG, data);
         break;
       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
+        tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
         break;
       case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
+        tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
         break;
       case ASI_IMMU_CTXT_NONZERO_CONFIG:
         assert(va == 0);
-        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
+        tc->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG, data);
         break;
       case ASI_SPARC_ERROR_EN_REG:
       case ASI_SPARC_ERROR_STATUS_REG:
@@ -1121,16 +1121,16 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
         break;
       case ASI_HYP_SCRATCHPAD:
       case ASI_SCRATCHPAD:
-        tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
+        tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
         break;
       case ASI_IMMU:
         switch (va) {
           case 0x18:
-            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
+            tc->setMiscReg(MISCREG_MMU_ITLB_SFSR, data);
             break;
           case 0x30:
             sext<59>(bits(data, 59,0));
-            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
+            tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, data);
             break;
           default:
             goto doMmuWriteError;
@@ -1140,10 +1140,10 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
         entry_insert = bits(va, 8,3);
       case ASI_ITLB_DATA_IN_REG:
         assert(entry_insert != -1 || mbits(va,10,9) == va);
-        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
+        ta_insert = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS);
         va_insert = mbits(ta_insert, 63,13);
         ct_insert = mbits(ta_insert, 12,0);
-        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
+        part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
         real_insert = bits(va, 9,9);
         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
                 PageTableEntry::sun4u);
@@ -1154,10 +1154,10 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
         entry_insert = bits(va, 8,3);
       case ASI_DTLB_DATA_IN_REG:
         assert(entry_insert != -1 || mbits(va,10,9) == va);
-        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
+        ta_insert = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS);
         va_insert = mbits(ta_insert, 63,13);
         ct_insert = mbits(ta_insert, 12,0);
-        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
+        part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
         real_insert = bits(va, 9,9);
         pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
                 PageTableEntry::sun4u);
@@ -1166,10 +1166,10 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
       case ASI_IMMU_DEMAP:
         ignore = false;
         ctx_id = -1;
-        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
+        part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
         switch (bits(va,5,4)) {
           case 0:
-            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
+            ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
             break;
           case 1:
             ignore = true;
@@ -1201,14 +1201,14 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
       case ASI_DMMU:
         switch (va) {
           case 0x18:
-            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
+            tc->setMiscReg(MISCREG_MMU_DTLB_SFSR, data);
             break;
           case 0x30:
             sext<59>(bits(data, 59,0));
-            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
+            tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, data);
             break;
           case 0x80:
-            tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
+            tc->setMiscReg(MISCREG_MMU_PART_ID, data);
             break;
           default:
             goto doMmuWriteError;
@@ -1217,13 +1217,13 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
       case ASI_DMMU_DEMAP:
         ignore = false;
         ctx_id = -1;
-        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
+        part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
         switch (bits(va,5,4)) {
           case 0:
-            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
+            ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
             break;
           case 1:
-            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
+            ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
             break;
           case 3:
             ctx_id = 0;
@@ -1274,25 +1274,25 @@ DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
 {
     uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
     ptrs[0] = MakeTsbPtr(Ps0, tag_access,
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
+                tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0),
+                tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0),
+                tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
     ptrs[1] = MakeTsbPtr(Ps1, tag_access,
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
+                tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
     ptrs[2] = MakeTsbPtr(Ps0, tag_access,
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0),
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
     ptrs[3] = MakeTsbPtr(Ps1, tag_access,
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1),
-                tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1),
+                tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
 }
 
 
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 5b13cd041..7a16dc352 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -66,18 +66,18 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
     switch (miscReg) {
         /* Full system only ASRs */
       case MISCREG_SOFTINT:
-        setReg(miscReg, val);;
+        setRegNoEffect(miscReg, val);;
         checkSoftInt(tc);
         break;
       case MISCREG_SOFTINT_CLR:
-        return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
+        return setReg(MISCREG_SOFTINT, ~val & softint, tc);
       case MISCREG_SOFTINT_SET:
-        return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
+        return setReg(MISCREG_SOFTINT, val | softint, tc);
 
       case MISCREG_TICK_CMPR:
         if (tickCompare == NULL)
             tickCompare = new TickCompareEvent(this, tc);
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
             tickCompare->deschedule();
         time = (tick_cmpr & mask(63)) - (tick & mask(63));
@@ -92,7 +92,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
       case MISCREG_STICK_CMPR:
         if (sTickCompare == NULL)
             sTickCompare = new STickCompareEvent(this, tc);
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
             sTickCompare->deschedule();
         time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
@@ -106,10 +106,10 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         break;
 
       case MISCREG_PSTATE:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
 
       case MISCREG_PIL:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         checkSoftInt(tc);
         break;
 
@@ -117,7 +117,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         panic("Shouldn't be writing HVER\n");
 
       case MISCREG_HINTP:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if (hintp)
             tc->getCpuPtr()->post_interrupt(IT_HINTP,0);
         else
@@ -126,12 +126,12 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
 
       case MISCREG_HTBA:
         // clear lower 7 bits on writes.
-        setReg(miscReg, val & ULL(~0x7FFF));
+        setRegNoEffect(miscReg, val & ULL(~0x7FFF));
         break;
 
       case MISCREG_QUEUE_CPU_MONDO_HEAD:
       case MISCREG_QUEUE_CPU_MONDO_TAIL:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if (cpu_mondo_head != cpu_mondo_tail)
             tc->getCpuPtr()->post_interrupt(IT_CPU_MONDO,0);
         else
@@ -139,7 +139,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         break;
       case MISCREG_QUEUE_DEV_MONDO_HEAD:
       case MISCREG_QUEUE_DEV_MONDO_TAIL:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if (dev_mondo_head != dev_mondo_tail)
             tc->getCpuPtr()->post_interrupt(IT_DEV_MONDO,0);
         else
@@ -147,7 +147,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         break;
       case MISCREG_QUEUE_RES_ERROR_HEAD:
       case MISCREG_QUEUE_RES_ERROR_TAIL:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if (res_error_head != res_error_tail)
             tc->getCpuPtr()->post_interrupt(IT_RES_ERROR,0);
         else
@@ -155,14 +155,14 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         break;
       case MISCREG_QUEUE_NRES_ERROR_HEAD:
       case MISCREG_QUEUE_NRES_ERROR_TAIL:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         // This one doesn't have an interrupt to report to the guest OS
         break;
 
       case MISCREG_HSTICK_CMPR:
         if (hSTickCompare == NULL)
             hSTickCompare = new HSTickCompareEvent(this, tc);
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
             hSTickCompare->deschedule();
         time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
@@ -177,7 +177,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
 
       case MISCREG_HPSTATE:
         // T1000 spec says impl. dependent val must always be 1
-        setReg(miscReg, val | HPSTATE::id);
+        setRegNoEffect(miscReg, val | HPSTATE::id);
 #if FULL_SYSTEM
         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
             tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
@@ -187,7 +187,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         break;
       case MISCREG_HTSTATE:
       case MISCREG_STRAND_STS_REG:
-        setReg(miscReg, val);
+        setRegNoEffect(miscReg, val);
         break;
 
       default:
@@ -217,10 +217,10 @@ MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
       case MISCREG_HTSTATE:
       case MISCREG_STRAND_STS_REG:
       case MISCREG_HSTICK_CMPR:
-        return readReg(miscReg) ;
+        return readRegNoEffect(miscReg) ;
 
       case MISCREG_HTBA:
-        return readReg(miscReg) & ULL(~0x7FFF);
+        return readRegNoEffect(miscReg) & ULL(~0x7FFF);
       case MISCREG_HVER:
         return NWindows | MaxTL << 8 | MaxGL << 16;
 
@@ -259,8 +259,8 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
     if (ticks == 0) {
         DPRINTF(Timer, "STick compare cycle reached at %#x\n",
                 (stick_cmpr & mask(63)));
-        if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
-            setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
+        if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
+            setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
         }
     } else
         sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
@@ -280,8 +280,8 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
     if (ticks == 0) {
         DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
                 (stick_cmpr & mask(63)));
-        if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
-            setRegWithEffect(MISCREG_HINTP, 1, tc);
+        if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
+            setReg(MISCREG_HINTP, 1, tc);
         }
         // Need to do something to cause interrupt to happen here !!! @todo
     } else
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 3c8bdcd01..64b91695e 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -44,8 +44,8 @@ namespace SparcISA
     static inline bool
     inUserMode(ThreadContext *tc)
     {
-        return !(tc->readMiscReg(MISCREG_PSTATE & (1 << 2)) ||
-                tc->readMiscReg(MISCREG_HPSTATE & (1 << 2)));
+        return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) ||
+                tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
     }
 
     inline ExtMachInst
@@ -56,7 +56,7 @@ namespace SparcISA
         //slightly redundant, but it removes the need to put a condition
         //into all the execute functions
         if(inst & (1 << 13))
-            emi |= (static_cast<ExtMachInst>(xc->readMiscReg(MISCREG_ASI))
+            emi |= (static_cast<ExtMachInst>(xc->readMiscRegNoEffect(MISCREG_ASI))
                     << (sizeof(MachInst) * 8));
         else
             emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc
index cb545185a..9a93950d2 100644
--- a/src/arch/sparc/vtophys.cc
+++ b/src/arch/sparc/vtophys.cc
@@ -66,7 +66,7 @@ namespace SparcISA
         // 4. We are not priv, use ctxN0* tsbs to find the page
         // For all accesses we check the tlbs first since it's possible that
         // long standing pages (e.g. locked kernel mappings) won't be in the tsb
-        uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
+        uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
 
         bool hpriv = bits(tlbdata,0,0);
         //bool priv = bits(tlbdata,2,2);