Clock: Add a Cycles wrapper class and use where applicable

This patch addresses the comments and feedback on the preceding patch
that reworks the clocks and now more clearly shows where cycles
(relative cycle counts) are used to express time.

Instead of bumping the existing patch I chose to make this a separate
patch, merely to try and focus the discussion around a smaller set of
changes. The two patches will be pushed together though.

This changes done as part of this patch are mostly following directly
from the introduction of the wrapper class, and change enough code to
make things compile and run again. There are definitely more places
where int/uint/Tick is still used to represent cycles, and it will
take some time to chase them all down. Similarly, a lot of parameters
should be changed from Param.Tick and Param.Unsigned to
Param.Cycles.

In addition, the use of curTick is questionable as there should not be
an absolute cycle. Potential solutions can be built on top of this
patch. There is a similar situation in the o3 CPU where
lastRunningCycle is currently counting in Cycles, and is still an
absolute time. More discussion to be had in other words.

An additional change that would be appropriate in the future is to
perform a similar wrapping of Tick and probably also introduce a
Ticks class along with suitable operators for all these classes.

5 files changed, 22 insertions, 22 deletions

diff --git a/src/arch/sparc/mmapped_ipr.hh b/src/arch/sparc/mmapped_ipr.hh
index c13fdc910..153944e9d 100644
--- a/src/arch/sparc/mmapped_ipr.hh
+++ b/src/arch/sparc/mmapped_ipr.hh
@@ -44,13 +44,13 @@
 namespace SparcISA
 {
 
-inline Tick
+inline Cycles
 handleIprRead(ThreadContext *xc, Packet *pkt)
 {
     return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
 }
 
-inline Tick
+inline Cycles
 handleIprWrite(ThreadContext *xc, Packet *pkt)
 {
     return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 37f1479b0..9faf297d6 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -848,7 +848,7 @@ TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
     return NoFault;
 }
 
-Tick
+Cycles
 TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 {
     Addr va = pkt->getAddr();
@@ -1030,10 +1030,10 @@ doMmuReadError:
             (uint32_t)asi, va);
     }
     pkt->makeAtomicResponse();
-    return tc->getCpuPtr()->ticks(1);
+    return Cycles(1);
 }
 
-Tick
+Cycles
 TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
 {
     uint64_t data = pkt->get<uint64_t>();
@@ -1283,7 +1283,7 @@ doMmuWriteError:
             (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
     }
     pkt->makeAtomicResponse();
-    return tc->getCpuPtr()->ticks(1);
+    return Cycles(1);
 }
 
 void
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 89a049a8b..abbe2df3c 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -168,8 +168,8 @@ class TLB : public BaseTLB
      *  does not support the Checker model at the moment
      */
     Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
-    Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
-    Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
+    Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
+    Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
     void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
 
     // Checkpointing
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 5948e0713..d3708d861 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -114,7 +114,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         if (!(tick_cmpr & ~mask(63)) && time > 0) {
             if (tickCompare->scheduled())
                 cpu->deschedule(tickCompare);
-            cpu->schedule(tickCompare, curTick() + time * cpu->ticks(1));
+            cpu->schedule(tickCompare, cpu->clockEdge(Cycles(time)));
         }
         panic("writing to TICK compare register %#X\n", val);
         break;
@@ -130,7 +130,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         if (!(stick_cmpr & ~mask(63)) && time > 0) {
             if (sTickCompare->scheduled())
                 cpu->deschedule(sTickCompare);
-            cpu->schedule(sTickCompare, curTick() + time * cpu->ticks(1));
+            cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(time)));
         }
         DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
         break;
@@ -200,7 +200,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         if (!(hstick_cmpr & ~mask(63)) && time > 0) {
             if (hSTickCompare->scheduled())
                 cpu->deschedule(hSTickCompare);
-            cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1));
+            cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(time)));
         }
         DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
         break;
@@ -329,19 +329,19 @@ ISA::processSTickCompare(ThreadContext *tc)
     // since our microcode instructions take two cycles we need to check if
     // we're actually at the correct cycle or we need to wait a little while
     // more
-    int ticks;
-    ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
+    int delay;
+    delay = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
         cpu->instCount();
-    assert(ticks >= 0 && "stick compare missed interrupt cycle");
+    assert(delay >= 0 && "stick compare missed interrupt cycle");
 
-    if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
+    if (delay == 0 || tc->status() == ThreadContext::Suspended) {
         DPRINTF(Timer, "STick compare cycle reached at %#x\n",
                 (stick_cmpr & mask(63)));
         if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
             setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
         }
     } else {
-        cpu->schedule(sTickCompare, curTick() + ticks * cpu->ticks(1));
+        cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(delay)));
     }
 }
 
@@ -353,15 +353,15 @@ ISA::processHSTickCompare(ThreadContext *tc)
     // since our microcode instructions take two cycles we need to check if
     // we're actually at the correct cycle or we need to wait a little while
     // more
-    int ticks;
+    int delay;
     if ( tc->status() == ThreadContext::Halted)
        return;
 
-    ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
+    delay = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
         cpu->instCount();
-    assert(ticks >= 0 && "hstick compare missed interrupt cycle");
+    assert(delay >= 0 && "hstick compare missed interrupt cycle");
 
-    if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
+    if (delay == 0 || tc->status() == ThreadContext::Suspended) {
         DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
                 (stick_cmpr & mask(63)));
         if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
@@ -369,7 +369,7 @@ ISA::processHSTickCompare(ThreadContext *tc)
         }
         // Need to do something to cause interrupt to happen here !!! @todo
     } else {
-        cpu->schedule(hSTickCompare, curTick() + ticks * cpu->ticks(1));
+        cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(delay)));
     }
 }
 
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index b8e3b3f0e..285a40c26 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -77,7 +77,7 @@ startupCPU(ThreadContext *tc, int cpuId)
 {
     // Other CPUs will get activated by IPIs
     if (cpuId == 0 || !FullSystem)
-        tc->activate(0);
+        tc->activate(Cycles(0));
 }
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);