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authorGabe Black <gblack@eecs.umich.edu>2011-10-10 00:31:51 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-10-10 00:31:51 -0700
commit8eec565d0ddeb6a788bc084180b223757fd9d05f (patch)
treec97294ac68ae6ff9db4ba3c7acafd94d8aed5971 /src/arch/sparc
parent5bab52d56ddd482ae7eb1a6ae45d2a97fd457ca2 (diff)
downloadgem5-8eec565d0ddeb6a788bc084180b223757fd9d05f.tar.xz
SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/mmapped_ipr.hh8
-rw-r--r--src/arch/sparc/tlb.cc4
-rw-r--r--src/arch/sparc/tlb.hh2
3 files changed, 0 insertions, 14 deletions
diff --git a/src/arch/sparc/mmapped_ipr.hh b/src/arch/sparc/mmapped_ipr.hh
index 28e3ec259..68c73cac0 100644
--- a/src/arch/sparc/mmapped_ipr.hh
+++ b/src/arch/sparc/mmapped_ipr.hh
@@ -48,21 +48,13 @@ namespace SparcISA
inline Tick
handleIprRead(ThreadContext *xc, Packet *pkt)
{
-#if FULL_SYSTEM
return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
-#else
- panic("Shouldn't have a memory mapped register in SE\n");
-#endif
}
inline Tick
handleIprWrite(ThreadContext *xc, Packet *pkt)
{
-#if FULL_SYSTEM
return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
-#else
- panic("Shouldn't have a memory mapped register in SE\n");
-#endif
}
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index ddc37cf3b..6e390143b 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -840,8 +840,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
-#if FULL_SYSTEM
-
Tick
TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
{
@@ -1280,8 +1278,6 @@ doMmuWriteError:
return tc->getCpuPtr()->ticks(1);
}
-#endif
-
void
TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
{
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 76ef23b64..7d33f7044 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -167,10 +167,8 @@ class TLB : public BaseTLB
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
-#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
// Checkpointing