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| author | Lisa Hsu <hsul@eecs.umich.edu> | 2008-11-05 18:12:21 -0500 |
|---|---|---|
| committer | Lisa Hsu <hsul@eecs.umich.edu> | 2008-11-05 18:12:21 -0500 |
| commit | be679b8e5e67389095531e78d72306b9ec6d64aa (patch) | |
| tree | 0434797b751dd7f4ed25e38525c49ab4cd8c3518 /src/arch/sparc | |
| parent | 2435918ac28b1401fcd7bb1114e62a7a6f2310a9 (diff) | |
| parent | 44839d6b716f2eb25eabc57fe588a129e290e51c (diff) | |
| download | gem5-be679b8e5e67389095531e78d72306b9ec6d64aa.tar.xz | |
Automated merge with ssh://m5sim.org//repo/m5
Diffstat (limited to 'src/arch/sparc')
| -rw-r--r-- | src/arch/sparc/ua2005.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index 502033d97..2389c963d 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -257,7 +257,7 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc) temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative); // Check that the CPU array is fully populated // (by calling getNumCPus()) - assert(sys->getNumContexts() > tc->contextId()); + assert(sys->numContexts() > tc->contextId()); temp |= tc->contextId() << STS::shft_id; |