TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.

--HG--
extra : convert_revision : 2421af11f62f60fb48faeee6bddadac2987df0e8

2 files changed, 37 insertions, 42 deletions

diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 07d332b58..e201cef95 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -623,64 +623,32 @@ void PowerOnReset::invoke(ThreadContext * tc)
 void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc)
 {
     Process *p = tc->getProcessPtr();
-    Addr paddr;
-    bool success = p->pTable->translate(vaddr, paddr);
+    TlbEntry entry;
+    bool success = p->pTable->lookup(vaddr, entry);
     if(!success) {
         panic("Tried to execute unmapped address %#x.\n", vaddr);
     } else {
-
-        uint64_t entry = 0;
-        entry |= 0ULL << 1; // Not writable
-        entry |= 0ULL << 2; // Available in nonpriveleged mode
-        entry |= 0ULL << 3; // No side effects
-        entry |= 1ULL << 4; // Virtually cachable
-        entry |= 1ULL << 5; // Physically cachable
-        entry |= 0ULL << 6; // Not locked
-        entry |= mbits(paddr, 39, 13); // Physical address
-        entry |= 0ULL << 48; // size = 8k
-        entry |= 0uLL << 59; // Endianness not inverted
-        entry |= 0ULL << 60; // Not no fault only
-        entry |= 0ULL << 61; // size = 8k
-        entry |= 1ULL << 63; // valid
-        PageTableEntry PTE(entry);
-
         Addr alignedVaddr = p->pTable->pageAlign(vaddr);
         tc->getITBPtr()->insert(alignedVaddr, 0 /*partition id*/,
-                p->M5_pid /*context id*/, false, PTE);
+                p->M5_pid /*context id*/, false, entry.pte);
     }
 }
 
 void FastDataAccessMMUMiss::invoke(ThreadContext *tc)
 {
     Process *p = tc->getProcessPtr();
-    Addr paddr;
-    bool success = p->pTable->translate(vaddr, paddr);
+    TlbEntry entry;
+    bool success = p->pTable->lookup(vaddr, entry);
     if(!success) {
         p->checkAndAllocNextPage(vaddr);
-        success = p->pTable->translate(vaddr, paddr);
+        success = p->pTable->lookup(vaddr, entry);
     }
     if(!success) {
         panic("Tried to access unmapped address %#x.\n", vaddr);
     } else {
-
-        uint64_t entry = 0;
-        entry |= 1ULL << 1; // Writable
-        entry |= 0ULL << 2; // Available in nonpriveleged mode
-        entry |= 0ULL << 3; // No side effects
-        entry |= 1ULL << 4; // Virtually cachable
-        entry |= 1ULL << 5; // Physically cachable
-        entry |= 0ULL << 6; // Not locked
-        entry |= mbits(paddr, 39, 13); // Physical address
-        entry |= 0ULL << 48; // size = 8k
-        entry |= 0uLL << 59; // Endianness not inverted
-        entry |= 0ULL << 60; // Not no fault only
-        entry |= 0ULL << 61; // size = 8k
-        entry |= 1ULL << 63; // valid
-        PageTableEntry PTE(entry);
-
         Addr alignedVaddr = p->pTable->pageAlign(vaddr);
         tc->getDTBPtr()->insert(alignedVaddr, 0 /*partition id*/,
-                p->M5_pid /*context id*/, false, PTE);
+                p->M5_pid /*context id*/, false, entry.pte);
     }
 }
 
diff --git a/src/arch/sparc/pagetable.hh b/src/arch/sparc/pagetable.hh
index 961870579..bf7f34b60 100644
--- a/src/arch/sparc/pagetable.hh
+++ b/src/arch/sparc/pagetable.hh
@@ -190,16 +190,43 @@ struct TlbRange {
 
 
 struct TlbEntry {
-    Addr pageStart;
+    TlbEntry(Addr asn, Addr vaddr, Addr paddr)
+    {
+        uint64_t entry = 0;
+        entry |= 1ULL << 1; // Writable
+        entry |= 0ULL << 2; // Available in nonpriveleged mode
+        entry |= 0ULL << 3; // No side effects
+        entry |= 1ULL << 4; // Virtually cachable
+        entry |= 1ULL << 5; // Physically cachable
+        entry |= 0ULL << 6; // Not locked
+        entry |= mbits(paddr, 39, 13); // Physical address
+        entry |= 0ULL << 48; // size = 8k
+        entry |= 0uLL << 59; // Endianness not inverted
+        entry |= 0ULL << 60; // Not no fault only
+        entry |= 0ULL << 61; // size = 8k
+        entry |= 1ULL << 63; // valid
+        pte = PageTableEntry(entry);
+
+        range.va = vaddr;
+        range.size = 8*(1<<10);
+        range.contextId = asn;
+        range.partitionId = 0;
+        range.real = false;
+
+        valid = true;
+    }
     TlbEntry()
     {}
-    TlbEntry(Addr addr) : pageStart(addr)
-    {}
     TlbRange range;
     PageTableEntry pte;
     bool used;
     bool valid;
 
+    Addr pageStart()
+    {
+        return pte.paddr();
+    }
+
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);