Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.

Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.

src/arch/alpha/arguments.cc:
src/arch/alpha/arguments.hh:
src/arch/alpha/ev5.cc:
src/arch/alpha/faults.cc:
src/arch/alpha/faults.hh:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/freebsd/system.hh:
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/decoder.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/linux/system.hh:
src/arch/alpha/linux/threadinfo.hh:
src/arch/alpha/process.cc:
src/arch/alpha/regfile.hh:
src/arch/alpha/stacktrace.cc:
src/arch/alpha/stacktrace.hh:
src/arch/alpha/tlb.cc:
src/arch/alpha/tlb.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/system.cc:
src/arch/alpha/tru64/system.hh:
src/arch/alpha/utility.hh:
src/arch/alpha/vtophys.cc:
src/arch/alpha/vtophys.hh:
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/process.cc:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/regfile/regfile.hh:
src/arch/mips/stacktrace.hh:
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/regfile.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/stacktrace.hh:
src/arch/sparc/ua2005.cc:
src/arch/sparc/utility.hh:
src/arch/sparc/vtophys.cc:
src/arch/sparc/vtophys.hh:
src/base/remote_gdb.cc:
src/base/remote_gdb.hh:
src/cpu/base.cc:
src/cpu/base.hh:
src/cpu/base_dyn_inst.hh:
src/cpu/checker/cpu.cc:
src/cpu/checker/cpu.hh:
src/cpu/checker/exec_context.hh:
src/cpu/cpu_exec_context.cc:
src/cpu/cpu_exec_context.hh:
src/cpu/cpuevent.cc:
src/cpu/cpuevent.hh:
src/cpu/exetrace.hh:
src/cpu/intr_control.cc:
src/cpu/memtest/memtest.hh:
src/cpu/o3/alpha_cpu.hh:
src/cpu/o3/alpha_cpu_impl.hh:
src/cpu/o3/alpha_dyn_inst_impl.hh:
src/cpu/o3/commit.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/regfile.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/back_end.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/inorder_back_end.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_back_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/pc_event.cc:
src/cpu/pc_event.hh:
src/cpu/profile.cc:
src/cpu/profile.hh:
src/cpu/quiesce_event.cc:
src/cpu/quiesce_event.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
src/cpu/thread_state.hh:
src/dev/alpha_console.cc:
src/dev/ns_gige.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/kern/kernel_stats.cc:
src/kern/kernel_stats.hh:
src/kern/linux/events.cc:
src/kern/linux/events.hh:
src/kern/system_events.cc:
src/kern/system_events.hh:
src/kern/tru64/dump_mbuf.cc:
src/kern/tru64/tru64.hh:
src/kern/tru64/tru64_events.cc:
src/kern/tru64/tru64_events.hh:
src/mem/vport.cc:
src/mem/vport.hh:
src/sim/faults.cc:
src/sim/faults.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
src/sim/system.cc:
src/cpu/thread_context.hh:
src/sim/system.hh:
src/sim/vptr.hh:
    Change ExecContext to ThreadContext.

--HG--
rename : src/cpu/exec_context.hh => src/cpu/thread_context.hh
extra : convert_revision : 108bb97d15a114a565a2a6a23faa554f4e2fd77e

13 files changed, 114 insertions, 114 deletions

diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 09fdf230a..57b4d4d86 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -30,7 +30,7 @@
  */
 
 #include "arch/sparc/faults.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "cpu/base.hh"
 #include "base/trace.hh"
 
@@ -220,36 +220,36 @@ FaultStat     TrapInstruction::_count;
 
 #if FULL_SYSTEM
 
-void SparcFault::invoke(ExecContext * xc)
+void SparcFault::invoke(ThreadContext * tc)
 {
-    FaultBase::invoke(xc);
+    FaultBase::invoke(tc);
     countStat()++;
 
     //Use the SPARC trap state machine
     /*// exception restart address
-    if (setRestartAddress() || !xc->inPalMode())
-        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
+    if (setRestartAddress() || !tc->inPalMode())
+        tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->regs.pc);
 
     if (skipFaultingInstruction()) {
         // traps...  skip faulting instruction.
-        xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
-                   xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
+        tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
+                   tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
     }
 
-    if (!xc->inPalMode())
-        AlphaISA::swap_palshadow(&(xc->regs), true);
+    if (!tc->inPalMode())
+        AlphaISA::swap_palshadow(&(tc->regs), true);
 
-    xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
-    xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/
+    tc->regs.pc = tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
+    tc->regs.npc = tc->regs.pc + sizeof(MachInst);*/
 }
 
 #endif
 
 #if !FULL_SYSTEM
 
-void TrapInstruction::invoke(ExecContext * xc)
+void TrapInstruction::invoke(ThreadContext * tc)
 {
-    xc->syscall(syscall_num);
+    tc->syscall(syscall_num);
 }
 
 #endif
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 88efe2eee..9f595a28b 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -46,7 +46,7 @@ class SparcFault : public FaultBase
 {
   public:
 #if FULL_SYSTEM
-    void invoke(ExecContext * xc);
+    void invoke(ThreadContext * tc);
 #endif
     virtual TrapType trapType() = 0;
     virtual FaultPriority priority() = 0;
@@ -585,7 +585,7 @@ class TrapInstruction : public EnumeratedFault
     FaultPriority priority() {return _priority;}
     FaultStat & countStat() {return _count;}
 #if !FULL_SYSTEM
-    void invoke(ExecContext * xc);
+    void invoke(ThreadContext * tc);
 #endif
 };
 
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index d4fcbb522..346f7b730 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -36,7 +36,7 @@
 #include "config/full_system.hh"
 #include "sim/host.hh"
 
-class ExecContext;
+class ThreadContext;
 class FastCPU;
 //class FullCPU;
 class Checkpoint;
diff --git a/src/arch/sparc/linux/process.cc b/src/arch/sparc/linux/process.cc
index db9a32c28..e27255e67 100644
--- a/src/arch/sparc/linux/process.cc
+++ b/src/arch/sparc/linux/process.cc
@@ -35,7 +35,7 @@
 #include "arch/sparc/regfile.hh"
 
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "kern/linux/linux.hh"
 
 #include "sim/process.hh"
@@ -48,9 +48,9 @@ using namespace SparcISA;
 /// Target uname() handler.
 static SyscallReturn
 unameFunc(SyscallDesc *desc, int callnum, Process *process,
-          ExecContext *xc)
+          ThreadContext *tc)
 {
-    TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
+    TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0));
 
     strcpy(name->sysname, "Linux");
     strcpy(name->nodename, "m5.eecs.umich.edu");
@@ -58,40 +58,40 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "sparc");
 
-    name.copyOut(xc->getMemPort());
+    name.copyOut(tc->getMemPort());
 
     return 0;
 }
 
 
 SyscallReturn SparcISA::getresuidFunc(SyscallDesc *desc, int num,
-                                         Process *p, ExecContext *xc)
+                                         Process *p, ThreadContext *tc)
 {
     const IntReg id = htog(100);
-    Addr ruid = xc->getSyscallArg(0);
-    Addr euid = xc->getSyscallArg(1);
-    Addr suid = xc->getSyscallArg(2);
+    Addr ruid = tc->getSyscallArg(0);
+    Addr euid = tc->getSyscallArg(1);
+    Addr suid = tc->getSyscallArg(2);
     //Handle the EFAULT case
     //Set the ruid
     if(ruid)
     {
         BufferArg ruidBuff(ruid, sizeof(IntReg));
         memcpy(ruidBuff.bufferPtr(), &id, sizeof(IntReg));
-        ruidBuff.copyOut(xc->getMemPort());
+        ruidBuff.copyOut(tc->getMemPort());
     }
     //Set the euid
     if(euid)
     {
         BufferArg euidBuff(euid, sizeof(IntReg));
         memcpy(euidBuff.bufferPtr(), &id, sizeof(IntReg));
-        euidBuff.copyOut(xc->getMemPort());
+        euidBuff.copyOut(tc->getMemPort());
     }
     //Set the suid
     if(suid)
     {
         BufferArg suidBuff(suid, sizeof(IntReg));
         memcpy(suidBuff.bufferPtr(), &id, sizeof(IntReg));
-        suidBuff.copyOut(xc->getMemPort());
+        suidBuff.copyOut(tc->getMemPort());
     }
     return 0;
 }
diff --git a/src/arch/sparc/linux/process.hh b/src/arch/sparc/linux/process.hh
index cd59e4fd2..f4819ba84 100644
--- a/src/arch/sparc/linux/process.hh
+++ b/src/arch/sparc/linux/process.hh
@@ -61,7 +61,7 @@ class SparcLinuxProcess : public SparcLiveProcess
 };
 
 SyscallReturn getresuidFunc(SyscallDesc *desc, int num,
-                                 Process *p, ExecContext *xc);
+                                 Process *p, ThreadContext *tc);
 
 } // namespace SparcISA
 #endif // __ALPHA_LINUX_PROCESS_HH__
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index 4b18dcca9..633c202ca 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -35,7 +35,7 @@
 #include "arch/sparc/solaris/process.hh"
 #include "base/loader/object_file.hh"
 #include "base/misc.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
 #include "mem/translating_port.hh"
 #include "sim/builder.hh"
@@ -113,27 +113,27 @@ SparcLiveProcess::startup()
     //From the SPARC ABI
 
     //The process runs in user mode
-    execContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02);
+    threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02);
 
     //Setup default FP state
-    execContexts[0]->setMiscReg(MISCREG_FSR, 0);
+    threadContexts[0]->setMiscReg(MISCREG_FSR, 0);
 
-    execContexts[0]->setMiscReg(MISCREG_TICK, 0);
+    threadContexts[0]->setMiscReg(MISCREG_TICK, 0);
     //
     /*
      * Register window management registers
      */
 
     //No windows contain info from other programs
-    execContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0);
+    threadContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0);
     //There are no windows to pop
-    execContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0);
+    threadContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0);
     //All windows are available to save into
-    execContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2);
+    threadContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2);
     //All windows are "clean"
-    execContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows);
+    threadContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows);
     //Start with register window 0
-    execContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0);
+    threadContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0);
 }
 
 m5_auxv_t buildAuxVect(int64_t type, int64_t val)
@@ -311,14 +311,14 @@ SparcLiveProcess::argsInit(int intSize, int pageSize)
 
     initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
 
-    execContexts[0]->setIntReg(ArgumentReg0, argc);
-    execContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
-    execContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);
+    threadContexts[0]->setIntReg(ArgumentReg0, argc);
+    threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
+    threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);
 
     Addr prog_entry = objFile->entryPoint();
-    execContexts[0]->setPC(prog_entry);
-    execContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
-    execContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
+    threadContexts[0]->setPC(prog_entry);
+    threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
+    threadContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
 
 //    num_processes++;
 }
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index 2739048eb..aaf1fcf24 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -563,9 +563,9 @@ namespace SparcISA
 #if FULL_SYSTEM
         /** Process a tick compare event and generate an interrupt on the cpu if
          * appropriate. */
-        void processTickCompare(ExecContext *xc);
-        void processSTickCompare(ExecContext *xc);
-        void processHSTickCompare(ExecContext *xc);
+        void processTickCompare(ThreadContext *tc);
+        void processSTickCompare(ThreadContext *tc);
+        void processHSTickCompare(ThreadContext *tc);
 
         typedef CpuEventWrapper<MiscRegFile,
                 &MiscRegFile::processTickCompare> TickCompareEvent;
@@ -580,10 +580,10 @@ namespace SparcISA
         HSTickCompareEvent *hSTickCompare;
 
         /** Fullsystem only register version of ReadRegWithEffect() */
-        MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ExecContext *xc);
+        MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
         /** Fullsystem only register version of SetRegWithEffect() */
         Fault setFSRegWithEffect(int miscReg, const MiscReg &val,
-                ExecContext * xc);
+                ThreadContext * tc);
 #endif
       public:
 
@@ -657,7 +657,7 @@ namespace SparcISA
          * are are readFSRegWithEffect (which is called by readRegWithEffect()).
          * Checking is done for permission based on state bits in the miscreg
          * file. */
-        MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc);
+        MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
 
         /** write a value into an either an SE or FS IPR. No checking is done
          * about SE vs. FS as this is mostly used to copy the regfile. Thus more
@@ -671,13 +671,13 @@ namespace SparcISA
          * Checking is done for permission based on state bits in the miscreg
          * file. */
         Fault setRegWithEffect(int miscReg,
-                const MiscReg &val, ExecContext * xc);
+                const MiscReg &val, ThreadContext * tc);
 
         void serialize(std::ostream & os);
 
         void unserialize(Checkpoint * cp, const std::string & section);
 
-        void copyMiscRegs(ExecContext * xc);
+        void copyMiscRegs(ThreadContext * tc);
 
         bool isHyperPriv() { return hpstateFields.hpriv; }
         bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
@@ -753,9 +753,9 @@ namespace SparcISA
         }
 
         MiscReg readMiscRegWithEffect(int miscReg,
-                Fault &fault, ExecContext *xc)
+                Fault &fault, ThreadContext *tc)
         {
-            return miscRegFile.readRegWithEffect(miscReg, fault, xc);
+            return miscRegFile.readRegWithEffect(miscReg, fault, tc);
         }
 
         Fault setMiscReg(int miscReg, const MiscReg &val)
@@ -764,9 +764,9 @@ namespace SparcISA
         }
 
         Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
-                ExecContext * xc)
+                ThreadContext * tc)
         {
-            return miscRegFile.setRegWithEffect(miscReg, val, xc);
+            return miscRegFile.setRegWithEffect(miscReg, val, tc);
         }
 
         FloatReg readFloatReg(int floatReg, int width)
@@ -853,9 +853,9 @@ namespace SparcISA
         }
     };
 
-    void copyRegs(ExecContext *src, ExecContext *dest);
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
 
-    void copyMiscRegs(ExecContext *src, ExecContext *dest);
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 
     int InterruptLevel(uint64_t softint);
 
diff --git a/src/arch/sparc/solaris/process.cc b/src/arch/sparc/solaris/process.cc
index 74f77991d..af0550910 100644
--- a/src/arch/sparc/solaris/process.cc
+++ b/src/arch/sparc/solaris/process.cc
@@ -33,7 +33,7 @@
 #include "arch/sparc/regfile.hh"
 
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "kern/solaris/solaris.hh"
 
 #include "sim/process.hh"
@@ -46,9 +46,9 @@ using namespace SparcISA;
 /// Target uname() handler.
 static SyscallReturn
 unameFunc(SyscallDesc *desc, int callnum, Process *process,
-          ExecContext *xc)
+          ThreadContext *tc)
 {
-    TypedBufferArg<Solaris::utsname> name(xc->getSyscallArg(0));
+    TypedBufferArg<Solaris::utsname> name(tc->getSyscallArg(0));
 
     strcpy(name->sysname, "SunOS");
     strcpy(name->nodename, "m5.eecs.umich.edu");
@@ -56,7 +56,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
     strcpy(name->version, "Generic_118558-21");
     strcpy(name->machine, "sun4u");
 
-    name.copyOut(xc->getMemPort());
+    name.copyOut(tc->getMemPort());
 
     return 0;
 }
diff --git a/src/arch/sparc/stacktrace.hh b/src/arch/sparc/stacktrace.hh
index dd86a1553..d12aee211 100644
--- a/src/arch/sparc/stacktrace.hh
+++ b/src/arch/sparc/stacktrace.hh
@@ -34,13 +34,13 @@
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
 
-class ExecContext;
+class ThreadContext;
 class StackTrace;
 
 class ProcessInfo
 {
   private:
-    ExecContext *xc;
+    ThreadContext *tc;
 
     int thread_info_size;
     int task_struct_size;
@@ -49,7 +49,7 @@ class ProcessInfo
     int name_off;
 
   public:
-    ProcessInfo(ExecContext *_xc);
+    ProcessInfo(ThreadContext *_tc);
 
     Addr task(Addr ksp) const;
     int pid(Addr ksp) const;
@@ -61,7 +61,7 @@ class StackTrace
   protected:
     typedef TheISA::MachInst MachInst;
   private:
-    ExecContext *xc;
+    ThreadContext *tc;
     std::vector<Addr> stack;
 
   private:
@@ -70,21 +70,21 @@ class StackTrace
     bool decodeSave(MachInst inst, int &reg, int &disp);
     bool decodeStack(MachInst inst, int &disp);
 
-    void trace(ExecContext *xc, bool is_call);
+    void trace(ThreadContext *tc, bool is_call);
 
   public:
     StackTrace();
-    StackTrace(ExecContext *xc, StaticInstPtr inst);
+    StackTrace(ThreadContext *tc, StaticInstPtr inst);
     ~StackTrace();
 
     void clear()
     {
-        xc = 0;
+        tc = 0;
         stack.clear();
     }
 
-    bool valid() const { return xc != NULL; }
-    bool trace(ExecContext *xc, StaticInstPtr inst);
+    bool valid() const { return tc != NULL; }
+    bool trace(ThreadContext *tc, StaticInstPtr inst);
 
   public:
     const std::vector<Addr> &getstack() const { return stack; }
@@ -106,7 +106,7 @@ class StackTrace
 };
 
 inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
+StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
 {
     if (!inst->isCall() && !inst->isReturn())
         return false;
@@ -114,7 +114,7 @@ StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
     if (valid())
         clear();
 
-    trace(xc, !inst->isReturn());
+    trace(tc, !inst->isReturn());
     return true;
 }
 
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 9f4805058..b89d48663 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -32,7 +32,7 @@
 
 Fault
 SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
-        ExecContext *xc)
+        ThreadContext *tc)
 {
     int64_t time;
     SparcSystem *sys;
@@ -47,25 +47,25 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
           setReg(miscReg, val);
           if (newLevel > oldLevel)
               ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
-              //xc->getCpuPtr()->checkInterrupts = true;
+              //tc->getCpuPtr()->checkInterrupts = true;
           return NoFault;
 
         case MISCREG_SOFTINT_CLR:
-          return setRegWithEffect(miscReg, ~val & softint, xc);
+          return setRegWithEffect(miscReg, ~val & softint, tc);
         case MISCREG_SOFTINT_SET:
-          return setRegWithEffect(miscReg, val | softint, xc);
+          return setRegWithEffect(miscReg, val | softint, tc);
 
         case MISCREG_TICK_CMPR:
           if (isNonPriv())
               return new PrivilegedOpcode;
           if (tickCompare == NULL)
-              tickCompare = new TickCompareEvent(this, xc);
+              tickCompare = new TickCompareEvent(this, tc);
           setReg(miscReg, val);
           if (tick_cmprFields.int_dis && tickCompare.scheduled())
                   tickCompare.deschedule();
           time = tick_cmprFields.tick_cmpr - tickFields.counter;
           if (!tick_cmprFields.int_dis && time > 0)
-              tickCompare.schedule(time * xc->getCpuPtr()->cycles(1));
+              tickCompare.schedule(time * tc->getCpuPtr()->cycles(1));
           return NoFault;
 
         case MISCREG_STICK:
@@ -73,7 +73,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
               return new PrivilegedOpcode;
           if (isPriv())
               return new PrivilegedAction;
-          sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
+          sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
           assert(sys != NULL);
           sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
           stickFields.npt = val & Bit64 ? 1 : 0;
@@ -83,8 +83,8 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
           if (isNonPriv())
               return new PrivilegedOpcode;
           if (sTickCompare == NULL)
-              sTickCompare = new STickCompareEvent(this, xc);
-          sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
+              sTickCompare = new STickCompareEvent(this, tc);
+          sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
           assert(sys != NULL);
           setReg(miscReg, val);
           if (stick_cmprFields.int_dis && sTickCompare.scheduled())
@@ -98,7 +98,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
         case MISCREG_PIL:
           if (FULL_SYSTEM) {
               setReg(miscReg, val);
-              //xc->getCpuPtr()->checkInterrupts;
+              //tc->getCpuPtr()->checkInterrupts;
                // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
               return NoFault;
           } else
@@ -127,8 +127,8 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
           if (isNonPriv())
               return new PrivilegedOpcode;
           if (hSTickCompare == NULL)
-              hSTickCompare = new HSTickCompareEvent(this, xc);
-          sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
+              hSTickCompare = new HSTickCompareEvent(this, tc);
+          sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
           assert(sys != NULL);
           setReg(miscReg, val);
           if (hstick_cmprFields.int_dis && hSTickCompare.scheduled())
@@ -143,7 +143,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
 }
 
 MiscReg
-MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc)
+MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc)
 {
     switch (miscReg) {
 
@@ -166,7 +166,7 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc)
               fault = new PrivilegedAction;
               return 0;
           }
-          sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
+          sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
           assert(sys != NULL);
           return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
         case MISCREG_STICK_CMPR:
@@ -204,19 +204,19 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc)
 }
 
 void
-MiscRegFile::processTickCompare(ExecContext *xc)
+MiscRegFile::processTickCompare(ThreadContext *tc)
 {
     panic("tick compare not implemented\n");
 }
 
 void
-MiscRegFile::processSTickCompare(ExecContext *xc)
+MiscRegFile::processSTickCompare(ThreadContext *tc)
 {
     panic("tick compare not implemented\n");
 }
 
 void
-MiscRegFile::processHSTickCompare(ExecContext *xc)
+MiscRegFile::processHSTickCompare(ThreadContext *tc)
 {
     panic("tick compare not implemented\n");
 }
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index f75beb04a..f1c071148 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -81,10 +81,10 @@ namespace SparcISA
 
     /**
      * Function to insure ISA semantics about 0 registers.
-     * @param xc The execution context.
+     * @param tc The thread context.
      */
-    template <class XC>
-    void zeroRegisters(XC *xc);
+    template <class TC>
+    void zeroRegisters(TC *tc);
 
 } // namespace SparcISA
 
diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc
index 0c69ea0a9..f7fd92c15 100644
--- a/src/arch/sparc/vtophys.cc
+++ b/src/arch/sparc/vtophys.cc
@@ -36,7 +36,7 @@
 #include "arch/alpha/vtophys.hh"
 #include "base/chunk_generator.hh"
 #include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
 #include "mem/vport.hh"
 
 using namespace std;
@@ -85,10 +85,10 @@ AlphaISA::vtophys(Addr vaddr)
 }
 
 Addr
-AlphaISA::vtophys(ExecContext *xc, Addr addr)
+AlphaISA::vtophys(ThreadContext *tc, Addr addr)
 {
     AlphaISA::VAddr vaddr = addr;
-    Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20);
+    Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20);
     Addr paddr = 0;
     //@todo Andrew couldn't remember why he commented some of this code
     //so I put it back in. Perhaps something to do with gdb debugging?
@@ -101,7 +101,7 @@ AlphaISA::vtophys(ExecContext *xc, Addr addr)
             paddr = vaddr;
         } else {
             AlphaISA::PageTableEntry pte =
-                kernel_pte_lookup(xc->getPhysPort(), ptbr, vaddr);
+                kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr);
             if (pte.valid())
                 paddr = pte.paddr() | vaddr.offset();
         }
@@ -115,52 +115,52 @@ AlphaISA::vtophys(ExecContext *xc, Addr addr)
 
 
 void
-AlphaISA::CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
+AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
 {
     uint8_t *dst = (uint8_t *)dest;
-    VirtualPort *vp = xc->getVirtPort(xc);
+    VirtualPort *vp = tc->getVirtPort(tc);
 
     vp->readBlob(src, dst, cplen);
 
-    xc->delVirtPort(vp);
+    tc->delVirtPort(vp);
 
 }
 
 void
-AlphaISA::CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
+AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
 {
     uint8_t *src = (uint8_t *)source;
-    VirtualPort *vp = xc->getVirtPort(xc);
+    VirtualPort *vp = tc->getVirtPort(tc);
 
     vp->writeBlob(dest, src, cplen);
 
-    xc->delVirtPort(vp);
+    tc->delVirtPort(vp);
 }
 
 void
-AlphaISA::CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
+AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
 {
     int len = 0;
-    VirtualPort *vp = xc->getVirtPort(xc);
+    VirtualPort *vp = tc->getVirtPort(tc);
 
     do {
         vp->readBlob(vaddr++, (uint8_t*)dst++, 1);
         len++;
     } while (len < maxlen && dst[len] != 0 );
 
-    xc->delVirtPort(vp);
+    tc->delVirtPort(vp);
     dst[len] = 0;
 }
 
 void
-AlphaISA::CopyStringIn(ExecContext *xc, char *src, Addr vaddr)
+AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
 {
-    VirtualPort *vp = xc->getVirtPort(xc);
+    VirtualPort *vp = tc->getVirtPort(tc);
     for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done();
             gen.next())
     {
         vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size());
         src += gen.size();
     }
-    xc->delVirtPort(vp);
+    tc->delVirtPort(vp);
 }
diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh
index d9b1a25c9..bf2b757d6 100644
--- a/src/arch/sparc/vtophys.hh
+++ b/src/arch/sparc/vtophys.hh
@@ -34,7 +34,7 @@
 
 #include "arch/sparc/isa_traits.hh"
 
-class ExecContext;
+class ThreadContext;
 class FunctionalPort;
 
 namespace SparcISA {
@@ -43,12 +43,12 @@ PageTableEntry
 kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr);
 
 Addr vtophys(Addr vaddr);
-Addr vtophys(ExecContext *xc, Addr vaddr);
+Addr vtophys(ThreadContext *tc, Addr vaddr);
 
-void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len);
-void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len);
-void CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen);
-void CopyStringIn(ExecContext *xc, char *src, Addr vaddr);
+void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len);
+void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len);
+void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
+void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
 
 };
 #endif // __ARCH_SPARC_VTOPHYS_H__