style: Use the correct m5 style for things relating to interrupts.

4 files changed, 45 insertions, 36 deletions

diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh
index 7d1496d8e..66b3792b5 100644
--- a/src/arch/sparc/interrupts.hh
+++ b/src/arch/sparc/interrupts.hh
@@ -45,7 +45,6 @@ class Interrupts : public SimObject
 {
 
   private:
-
     uint64_t interrupts[NumInterruptTypes];
     uint64_t intStatus;
 
@@ -60,10 +59,11 @@ class Interrupts : public SimObject
 
     Interrupts(Params * p) : SimObject(p)
     {
-        clear_all();
+        clearAll();
     }
 
-    int InterruptLevel(uint64_t softint)
+    int
+    InterruptLevel(uint64_t softint)
     {
         if (softint & 0x10000 || softint & 0x1)
             return 14;
@@ -76,7 +76,8 @@ class Interrupts : public SimObject
         return 0;
     }
 
-    void post(int int_num, int index)
+    void
+    post(int int_num, int index)
     {
         DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
         assert(int_num >= 0 && int_num < NumInterruptTypes);
@@ -86,7 +87,8 @@ class Interrupts : public SimObject
         intStatus |= ULL(1) << int_num;
     }
 
-    void clear(int int_num, int index)
+    void
+    clear(int int_num, int index)
     {
         DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
         assert(int_num >= 0 && int_num < NumInterruptTypes);
@@ -97,7 +99,8 @@ class Interrupts : public SimObject
             intStatus &= ~(ULL(1) << int_num);
     }
 
-    void clear_all()
+    void
+    clearAll()
     {
         for (int i = 0; i < NumInterruptTypes; ++i) {
             interrupts[i] = 0;
@@ -105,12 +108,14 @@ class Interrupts : public SimObject
         intStatus = 0;
     }
 
-    bool check_interrupts(ThreadContext * tc) const
+    bool
+    checkInterrupts(ThreadContext *tc) const
     {
         return intStatus;
     }
 
-    Fault getInterrupt(ThreadContext * tc)
+    Fault
+    getInterrupt(ThreadContext *tc)
     {
         int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
         int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
@@ -153,8 +158,8 @@ class Interrupts : public SimObject
                     return new DevMondo;
                 }
                 if (interrupts[IT_SOFT_INT]) {
-                    return new
-                        InterruptLevelN(InterruptLevel(interrupts[IT_SOFT_INT]));
+                    int level = InterruptLevel(interrupts[IT_SOFT_INT]);
+                    return new InterruptLevelN(level);
                 }
 
                 if (interrupts[IT_RES_ERROR]) {
@@ -165,24 +170,28 @@ class Interrupts : public SimObject
         return NoFault;
     }
 
-    void updateIntrInfo(ThreadContext * tc)
+    void
+    updateIntrInfo(ThreadContext *tc)
     {
 
     }
 
-    uint64_t get_vec(int int_num)
+    uint64_t
+    get_vec(int int_num)
     {
         assert(int_num >= 0 && int_num < NumInterruptTypes);
         return interrupts[int_num];
     }
 
-    void serialize(std::ostream &os)
+    void
+    serialize(std::ostream &os)
     {
         SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
         SERIALIZE_SCALAR(intStatus);
     }
 
-    void unserialize(Checkpoint *cp, const std::string &section)
+    void
+    unserialize(Checkpoint *cp, const std::string &section)
     {
         UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
         UNSERIALIZE_SCALAR(intStatus);
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index b0c5dbda9..b22ceb657 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -542,9 +542,9 @@ void MiscRegFile::setReg(int miscReg,
         tl = val;
 #if FULL_SYSTEM
         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
-            tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
+            tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
         else
-            tc->getCpuPtr()->clear_interrupt(IT_TRAP_LEVEL_ZERO,0);
+            tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
 #endif
         return;
       case MISCREG_CWP:
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 61f0985db..b6a450ffe 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1021,7 +1021,7 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
                 dynamic_cast<SparcISA::Interrupts *>(
                         tc->getCpuPtr()->getInterruptController());
             temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
-            tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
+            tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp);
             pkt->set(temp);
         }
         break;
@@ -1268,15 +1268,15 @@ DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
             SparcISA::Interrupts * interrupts =
                 dynamic_cast<SparcISA::Interrupts *>(
                         tc->getCpuPtr()->getInterruptController());
-            while(interrupts->get_vec(IT_INT_VEC) & data) {
+            while (interrupts->get_vec(IT_INT_VEC) & data) {
                 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
-                tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
+                tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb);
             }
         }
         break;
       case ASI_SWVR_UDB_INTR_W:
             tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
-            post_interrupt(bits(data,5,0),0);
+            postInterrupt(bits(data, 5, 0), 0);
         break;
       default:
 doMmuWriteError:
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 7b8524703..e1276b812 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -44,20 +44,20 @@ MiscRegFile::checkSoftInt(ThreadContext *tc)
 
     // If PIL < 14, copy over the tm and sm bits
     if (pil < 14 && softint & 0x10000)
-        cpu->post_interrupt(IT_SOFT_INT, 16);
+        cpu->postInterrupt(IT_SOFT_INT, 16);
     else
-        cpu->clear_interrupt(IT_SOFT_INT, 16);
+        cpu->clearInterrupt(IT_SOFT_INT, 16);
     if (pil < 14 && softint & 0x1)
-        cpu->post_interrupt(IT_SOFT_INT, 0);
+        cpu->postInterrupt(IT_SOFT_INT, 0);
     else
-        cpu->clear_interrupt(IT_SOFT_INT, 0);
+        cpu->clearInterrupt(IT_SOFT_INT, 0);
 
     // Copy over any of the other bits that are set
     for (int bit = 15; bit > 0; --bit) {
         if (1 << bit & softint && bit > pil)
-            cpu->post_interrupt(IT_SOFT_INT, bit);
+            cpu->postInterrupt(IT_SOFT_INT, bit);
         else
-            cpu->clear_interrupt(IT_SOFT_INT, bit);
+            cpu->clearInterrupt(IT_SOFT_INT, bit);
     }
 }
 
@@ -124,9 +124,9 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
       case MISCREG_HINTP:
         setRegNoEffect(miscReg, val);
         if (hintp)
-            cpu->post_interrupt(IT_HINTP, 0);
+            cpu->postInterrupt(IT_HINTP, 0);
         else
-            cpu->clear_interrupt(IT_HINTP, 0);
+            cpu->clearInterrupt(IT_HINTP, 0);
         break;
 
       case MISCREG_HTBA:
@@ -138,25 +138,25 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
       case MISCREG_QUEUE_CPU_MONDO_TAIL:
         setRegNoEffect(miscReg, val);
         if (cpu_mondo_head != cpu_mondo_tail)
-            cpu->post_interrupt(IT_CPU_MONDO, 0);
+            cpu->postInterrupt(IT_CPU_MONDO, 0);
         else
-            cpu->clear_interrupt(IT_CPU_MONDO, 0);
+            cpu->clearInterrupt(IT_CPU_MONDO, 0);
         break;
       case MISCREG_QUEUE_DEV_MONDO_HEAD:
       case MISCREG_QUEUE_DEV_MONDO_TAIL:
         setRegNoEffect(miscReg, val);
         if (dev_mondo_head != dev_mondo_tail)
-            cpu->post_interrupt(IT_DEV_MONDO, 0);
+            cpu->postInterrupt(IT_DEV_MONDO, 0);
         else
-            cpu->clear_interrupt(IT_DEV_MONDO, 0);
+            cpu->clearInterrupt(IT_DEV_MONDO, 0);
         break;
       case MISCREG_QUEUE_RES_ERROR_HEAD:
       case MISCREG_QUEUE_RES_ERROR_TAIL:
         setRegNoEffect(miscReg, val);
         if (res_error_head != res_error_tail)
-            cpu->post_interrupt(IT_RES_ERROR, 0);
+            cpu->postInterrupt(IT_RES_ERROR, 0);
         else
-            cpu->clear_interrupt(IT_RES_ERROR, 0);
+            cpu->clearInterrupt(IT_RES_ERROR, 0);
         break;
       case MISCREG_QUEUE_NRES_ERROR_HEAD:
       case MISCREG_QUEUE_NRES_ERROR_TAIL:
@@ -185,9 +185,9 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         setRegNoEffect(miscReg, val | HPSTATE::id);
 #if FULL_SYSTEM
         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
-            cpu->post_interrupt(IT_TRAP_LEVEL_ZERO, 0);
+            cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
         else
-            cpu->clear_interrupt(IT_TRAP_LEVEL_ZERO, 0);
+            cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
 #endif
         break;
       case MISCREG_HTSTATE: