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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-02-16 03:33:28 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-02-16 03:33:28 -0500 |
| commit | d0e1b8a19c6d58a49e5288938e9b12f3f10b9f51 (patch) | |
| tree | f990864e7fb9ffaf11e3895e8337737941390aa2 /src/arch/sparc | |
| parent | 07ce60bdfa57eedf00f533704b5a2da3fa01b553 (diff) | |
| download | gem5-d0e1b8a19c6d58a49e5288938e9b12f3f10b9f51.tar.xz | |
arch: Make readMiscRegNoEffect const throughout
Finally took the plunge and made this apply to all ISAs, not just ARM.
Diffstat (limited to 'src/arch/sparc')
| -rw-r--r-- | src/arch/sparc/isa.cc | 2 | ||||
| -rw-r--r-- | src/arch/sparc/isa.hh | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc index 4daf8775b..c9a3a33b4 100644 --- a/src/arch/sparc/isa.cc +++ b/src/arch/sparc/isa.cc @@ -173,7 +173,7 @@ ISA::clear() } MiscReg -ISA::readMiscRegNoEffect(int miscReg) +ISA::readMiscRegNoEffect(int miscReg) const { // The three miscRegs are moved up from the switch statement diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index 536deb69c..4551cf3c1 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -183,7 +183,7 @@ class ISA : public SimObject public: - MiscReg readMiscRegNoEffect(int miscReg); + MiscReg readMiscRegNoEffect(int miscReg) const; MiscReg readMiscReg(int miscReg, ThreadContext *tc); void setMiscRegNoEffect(int miscReg, const MiscReg val); |