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authorAli Saidi <saidi@eecs.umich.edu>2007-01-05 15:04:17 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-01-05 15:04:17 -0500
commit4a8078192d77f60580a79762156124e6331ea310 (patch)
treebad8c5223b34589e1d64abe43466bcbac1d659c0 /src/arch/sparc
parentb0f11f8f81b114739b70502066b9ff5e9f556b7b (diff)
downloadgem5-4a8078192d77f60580a79762156124e6331ea310.tar.xz
set the softint appropriately on an timer compare interrupt
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly src/arch/sparc/faults.cc: there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly src/arch/sparc/faults.hh: correct protection defines src/arch/sparc/ua2005.cc: set the softint appropriately on an timer compare interrupt --HG-- extra : convert_revision : f41c10ec78db973b3f856c70b58a17f83b60bbe2
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/faults.cc2
-rw-r--r--src/arch/sparc/faults.hh6
-rw-r--r--src/arch/sparc/ua2005.cc7
3 files changed, 8 insertions, 7 deletions
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 64cfc832a..af80238df 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -197,7 +197,7 @@ template<> SparcFaultBase::FaultVals
template<> SparcFaultBase::FaultVals
SparcFault<InterruptLevelN>::vals =
- {"interrupt_level_n", 0x041, 0, {P, P, SH}};
+ {"interrupt_level_n", 0x040, 0, {P, P, SH}};
template<> SparcFaultBase::FaultVals
SparcFault<HstickMatch>::vals =
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index e632502aa..6b3820ddd 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -29,8 +29,8 @@
* Kevin Lim
*/
-#ifndef __ALPHA_FAULTS_HH__
-#define __ALPHA_FAULTS_HH__
+#ifndef __SPARC_FAULTS_HH__
+#define __SPARC_FAULTS_HH__
#include "sim/faults.hh"
@@ -280,4 +280,4 @@ static inline Fault genAlignmentFault()
} // SparcISA namespace
-#endif // __FAULTS_HH__
+#endif // __SPARC_FAULTS_HH__
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 66d699fce..c7d2ffce5 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -73,7 +73,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
setReg(miscReg, val);
if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
sTickCompare->deschedule();
- time = ((int64_t)(stick_cmpr & mask(63)) + (int64_t)stick) -
+ time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
tc->getCpuPtr()->instCount();
if (!(stick_cmpr & ~mask(63)) && time > 0)
sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
@@ -197,14 +197,15 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
// we're actually at the correct cycle or we need to wait a little while
// more
int ticks;
- ticks = (stick_cmpr & mask(63)) - tc->getCpuPtr()->instCount();
+ ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
+ tc->getCpuPtr()->instCount();
assert(ticks >= 0 && "stick compare missed interrupt cycle");
if (ticks == 0) {
DPRINTF(Timer, "STick compare cycle reached at %#x\n",
(stick_cmpr & mask(63)));
tc->getCpuPtr()->checkInterrupts = true;
-
+ softint |= ULL(1) << 16;
} else
sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
}