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authorGabe Black <gblack@eecs.umich.edu>2010-08-23 16:14:20 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-08-23 16:14:20 -0700
commit943c1714803bb87d3b05b2516701dfb792996805 (patch)
treecfefb1ef949355bc237c9b6e37117b9b059e0116 /src/arch/sparc
parent9581562e653f6df810e40c076bc97d50daccf302 (diff)
downloadgem5-943c1714803bb87d3b05b2516701dfb792996805.tar.xz
ISA: Get rid of old, unused utility functions cluttering up the ISAs.
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/utility.hh38
1 files changed, 0 insertions, 38 deletions
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 064af9c6a..fe3082c5e 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -50,44 +50,6 @@ namespace SparcISA
(tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
}
- inline bool isCallerSaveIntegerRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- inline bool isCallerSaveFloatRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- inline bool isCalleeSaveFloatRegister(unsigned int reg) {
- panic("register classification not implemented");
- return false;
- }
-
- // Instruction address compression hooks
- inline Addr realPCToFetchPC(const Addr &addr)
- {
- return addr;
- }
-
- inline Addr fetchPCToRealPC(const Addr &addr)
- {
- return addr;
- }
-
- // the size of "fetched" instructions (not necessarily the size
- // of real instructions for PISA)
- inline size_t fetchInstSize()
- {
- return sizeof(MachInst);
- }
-
/**
* Function to insure ISA semantics about 0 registers.
* @param tc The thread context.