isa,cpu: Add support for FS SMT Interrupts

Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.

3 files changed, 24 insertions, 24 deletions

diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index a588eaf66..aa10a0b46 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -591,9 +591,9 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
         {
             tl = val;
             if (hpstate.tlz && tl == 0 && !hpstate.hpriv)
-                tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
+                tc->getCpuPtr()->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
             else
-                tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
+                tc->getCpuPtr()->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
             return;
         }
       case MISCREG_CWP:
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index c0c28f952..b4a761293 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1022,7 +1022,7 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
         {
             SparcISA::Interrupts * interrupts =
                 dynamic_cast<SparcISA::Interrupts *>(
-                        tc->getCpuPtr()->getInterruptController());
+                        tc->getCpuPtr()->getInterruptController(0));
             pkt->set(interrupts->get_vec(IT_INT_VEC));
         }
         break;
@@ -1030,9 +1030,9 @@ TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
         {
             SparcISA::Interrupts * interrupts =
                 dynamic_cast<SparcISA::Interrupts *>(
-                        tc->getCpuPtr()->getInterruptController());
+                        tc->getCpuPtr()->getInterruptController(0));
             temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
-            tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp);
+            tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp);
             pkt->set(temp);
         }
         break;
@@ -1278,16 +1278,16 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
             // clear all the interrupts that aren't set in the write
             SparcISA::Interrupts * interrupts =
                 dynamic_cast<SparcISA::Interrupts *>(
-                        tc->getCpuPtr()->getInterruptController());
+                        tc->getCpuPtr()->getInterruptController(0));
             while (interrupts->get_vec(IT_INT_VEC) & data) {
                 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
-                tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb);
+                tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb);
             }
         }
         break;
       case ASI_SWVR_UDB_INTR_W:
             tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
-            postInterrupt(bits(data, 5, 0), 0);
+            postInterrupt(0, bits(data, 5, 0), 0);
         break;
       default:
 doMmuWriteError:
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index b207f2fac..2c100957f 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -49,20 +49,20 @@ ISA::checkSoftInt(ThreadContext *tc)
 
     // If PIL < 14, copy over the tm and sm bits
     if (pil < 14 && softint & 0x10000)
-        cpu->postInterrupt(IT_SOFT_INT, 16);
+        cpu->postInterrupt(0, IT_SOFT_INT, 16);
     else
-        cpu->clearInterrupt(IT_SOFT_INT, 16);
+        cpu->clearInterrupt(0, IT_SOFT_INT, 16);
     if (pil < 14 && softint & 0x1)
-        cpu->postInterrupt(IT_SOFT_INT, 0);
+        cpu->postInterrupt(0, IT_SOFT_INT, 0);
     else
-        cpu->clearInterrupt(IT_SOFT_INT, 0);
+        cpu->clearInterrupt(0, IT_SOFT_INT, 0);
 
     // Copy over any of the other bits that are set
     for (int bit = 15; bit > 0; --bit) {
         if (1 << bit & softint && bit > pil)
-            cpu->postInterrupt(IT_SOFT_INT, bit);
+            cpu->postInterrupt(0, IT_SOFT_INT, bit);
         else
-            cpu->clearInterrupt(IT_SOFT_INT, bit);
+            cpu->clearInterrupt(0, IT_SOFT_INT, bit);
     }
 }
 
@@ -149,9 +149,9 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
       case MISCREG_HINTP:
         setMiscRegNoEffect(miscReg, val);
         if (hintp)
-            cpu->postInterrupt(IT_HINTP, 0);
+            cpu->postInterrupt(0, IT_HINTP, 0);
         else
-            cpu->clearInterrupt(IT_HINTP, 0);
+            cpu->clearInterrupt(0, IT_HINTP, 0);
         break;
 
       case MISCREG_HTBA:
@@ -163,25 +163,25 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
       case MISCREG_QUEUE_CPU_MONDO_TAIL:
         setMiscRegNoEffect(miscReg, val);
         if (cpu_mondo_head != cpu_mondo_tail)
-            cpu->postInterrupt(IT_CPU_MONDO, 0);
+            cpu->postInterrupt(0, IT_CPU_MONDO, 0);
         else
-            cpu->clearInterrupt(IT_CPU_MONDO, 0);
+            cpu->clearInterrupt(0, IT_CPU_MONDO, 0);
         break;
       case MISCREG_QUEUE_DEV_MONDO_HEAD:
       case MISCREG_QUEUE_DEV_MONDO_TAIL:
         setMiscRegNoEffect(miscReg, val);
         if (dev_mondo_head != dev_mondo_tail)
-            cpu->postInterrupt(IT_DEV_MONDO, 0);
+            cpu->postInterrupt(0, IT_DEV_MONDO, 0);
         else
-            cpu->clearInterrupt(IT_DEV_MONDO, 0);
+            cpu->clearInterrupt(0, IT_DEV_MONDO, 0);
         break;
       case MISCREG_QUEUE_RES_ERROR_HEAD:
       case MISCREG_QUEUE_RES_ERROR_TAIL:
         setMiscRegNoEffect(miscReg, val);
         if (res_error_head != res_error_tail)
-            cpu->postInterrupt(IT_RES_ERROR, 0);
+            cpu->postInterrupt(0, IT_RES_ERROR, 0);
         else
-            cpu->clearInterrupt(IT_RES_ERROR, 0);
+            cpu->clearInterrupt(0, IT_RES_ERROR, 0);
         break;
       case MISCREG_QUEUE_NRES_ERROR_HEAD:
       case MISCREG_QUEUE_NRES_ERROR_TAIL:
@@ -213,9 +213,9 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
             setMiscRegNoEffect(miscReg, newVal);
             newVal = hpstate;
             if (newVal.tlz && tl == 0 && !newVal.hpriv)
-                cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
+                cpu->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
             else
-                cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
+                cpu->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
             break;
         }
       case MISCREG_HTSTATE: