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authorAli Saidi <saidi@eecs.umich.edu>2006-12-18 03:37:52 -0500
committerAli Saidi <saidi@eecs.umich.edu>2006-12-18 03:37:52 -0500
commit6841f863c5dee6ce2028ba647254ec9ad27a57fd (patch)
tree816fc67716d4fc04ea85e1af77e64036c119539a /src/arch/sparc
parente65544b88b86c48bf8f65bd2ebc895a4ce90c6cc (diff)
downloadgem5-6841f863c5dee6ce2028ba647254ec9ad27a57fd.tar.xz
move the twinx loads to the correct opcode and add asis 0x24 and 0x27
Make the TLB ok to translate QUAD_LDD src/arch/sparc/isa/decoder.isa: move the twinx loads to the correct opcode. src/arch/sparc/tlb.cc: Make QUAD_LDD asi ok to execute --HG-- extra : convert_revision : 2a44d1c9e4edb627079fc05776c28d918c8508ce
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/isa/decoder.isa42
-rw-r--r--src/arch/sparc/tlb.cc3
2 files changed, 28 insertions, 17 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index bbc6a8c4b..e2bebd987 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1060,11 +1060,31 @@ decode OP default Unknown::unknown()
0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
- 0x13: ldtwa({{
- uint64_t val = Mem.udw;
- RdLow = val<31:0>;
- RdHigh = val<63:32>;
- }}, {{EXT_ASI}});
+ 0x13: decode EXT_ASI {
+ //ASI_QUAD_LDD
+ 0x24: TwinLoad::ldtx_quad_ldd(
+ {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+ //ASI_LDTX_REAL
+ 0x26: TwinLoad::ldtx_real(
+ {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+ //ASI_LDTX_N
+ 0x27: TwinLoad::ldtx_n(
+ {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+ //ASI_LDTX_L
+ 0x2C: TwinLoad::ldtx_l(
+ {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+ //ASI_LDTX_REAL_L
+ 0x2E: TwinLoad::ldtx_real_l(
+ {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+ //ASI_LDTX_N_L
+ 0x2F: TwinLoad::ldtx_n_l(
+ {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
+ default: ldtwa({{
+ uint64_t val = Mem.udw;
+ RdLow = val<31:0>;
+ RdHigh = val<63:32>;
+ }}, {{EXT_ASI}});
+ }
}
format StoreAlt {
0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
@@ -1126,18 +1146,6 @@ decode OP default Unknown::unknown()
0x15: FailUnimpl::lddfa_real_io();
//ASI_REAL_IO_LITTLE
0x1D: FailUnimpl::lddfa_real_io_l();
- //ASI_LDTX_REAL
- 0x26: TwinLoad::ldtx_real(
- {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
- //ASI_LDTX_N
- 0x27: TwinLoad::ldtx_n(
- {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
- //ASI_LDTX_REAL_L
- 0x2E: TwinLoad::ldtx_real_l(
- {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
- //ASI_LDTX_N_L
- 0x2F: TwinLoad::ldtx_n_l(
- {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
//ASI_PRIMARY
0x80: FailUnimpl::lddfa_p();
//ASI_PRIMARY_LITTLE
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 675287d18..1eb3aa53b 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -575,6 +575,9 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
if (write && asi == ASI_LDTX_P)
// block init store (like write hint64)
goto continueDtbFlow;
+ if (!write && asi == ASI_QUAD_LDD)
+ goto continueDtbFlow;
+
if (AsiIsTwin(asi))
panic("Twin ASIs not supported\n");
if (AsiIsPartialStore(asi))