add pseduo instruction support for sparc

util/m5/Makefile.alpha:
    Clean up to make it a bit easier to muck with
util/m5/Makefile.alpha:
    Make the makefile more reasonable
util/m5/Makefile.alpha:
    Remove authors from copyright.
util/m5/Makefile.alpha:
    Updated Authors from bk prs info
util/m5/Makefile.alpha:
    bk cp Makefile Makefile.alpha
src/arch/sparc/tlb.cc:
    Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate
src/arch/alpha/isa/decoder.isa:
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
    Rename AlphaPseudo -> PseudoInst since it's all generic
src/arch/sparc/isa/bitfields.isa:
src/arch/sparc/isa/decoder.isa:
src/arch/sparc/isa/includes.isa:
src/arch/sparc/isa/operands.isa:
    Add support for pseudo instructions in sparc
util/m5/Makefile.alpha:
util/m5/Makefile.sparc:
    split off alpha make file and sparc make file for m5 app
util/m5/m5.c:
    ivle and ivlb aren't used anymore
util/m5/m5op.h:
    stdint seems like a more generic better fit here
util/m5/m5op_alpha.S:
    move the op ids into their own header file since we can share them between sparc and alpha

--HG--
rename : util/m5/Makefile => util/m5/Makefile.sparc
rename : util/m5/m5op.S => util/m5/m5op_alpha.S
extra : convert_revision : 490ba2e8b8bc6e28bfc009cedec6b686b28e7834

5 files changed, 54 insertions, 18 deletions

diff --git a/src/arch/sparc/isa/bitfields.isa b/src/arch/sparc/isa/bitfields.isa
index e75680d2b..afa8f88a2 100644
--- a/src/arch/sparc/isa/bitfields.isa
+++ b/src/arch/sparc/isa/bitfields.isa
@@ -54,6 +54,7 @@ def bitfield FCN	<29:25>;
 def bitfield I		<13>;
 def bitfield IMM_ASI	<12:5>;
 def bitfield IMM22	<21:0>;
+def bitfield M5FUNC     <15:7>;
 def bitfield MMASK	<3:0>;
 def bitfield OP		<31:30>;
 def bitfield OP2	<24:22>;
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 0be7defba..e2d1707dd 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1009,7 +1009,16 @@ decode OP default Unknown::unknown()
                 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
                 0x81: FailUnimpl::siam();
             }
-            0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
+            // M5 special opcodes use the reserved IMPDEP2A opcode space
+            0x37: decode M5FUNC {
+                // we have 7 bits of space here to play with...
+                0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
+                              }}, No_OpClass, IsNonSpeculative);
+                0x54: m5panic({{
+                              panic("M5 panic instruction called at pc=%#x.", xc->readPC());
+                              }}, No_OpClass, IsNonSpeculative);
+
+            }
             0x38: Branch::jmpl({{
                 Addr target = Rs1 + Rs2_or_imm13;
                 if(target & 0x3)
@@ -1077,7 +1086,8 @@ decode OP default Unknown::unknown()
                     }
                 }}, IsSerializeAfter, IsNonSpeculative);
             }
-            0x3B: Nop::flush({{/*Instruction memory flush*/}});
+            0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
+                          MemWriteOp);
             0x3C: save({{
                 if(Cansave == 0)
                 {
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index b46ef011e..05e9e8731 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -70,6 +70,10 @@ output exec {{
 #include <ieeefp.h>
 #endif
 
+#if FULL_SYSTEM
+#include "sim/pseudo_inst.hh"
+#endif
+
 #include <limits>
 
 #include <cmath>
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index f624c3e2b..82e9407de 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -100,6 +100,12 @@ def operands {{
     'R1':  		('IntReg', 'udw', '1', None, 7),
     'R15': 		('IntReg', 'udw', '15', 'IsInteger', 8),
     'R16': 		('IntReg', 'udw', '16', None, 9),
+    'O0':               ('IntReg', 'udw', '24', 'IsInteger', 10),
+    'O1':               ('IntReg', 'udw', '25', 'IsInteger', 11),
+    'O2':               ('IntReg', 'udw', '26', 'IsInteger', 12),
+    'O3':               ('IntReg', 'udw', '27', 'IsInteger', 13),
+    'O4':               ('IntReg', 'udw', '28', 'IsInteger', 14),
+    'O5':               ('IntReg', 'udw', '29', 'IsInteger', 15),
 
     # Control registers
 #   'Y':		('ControlReg', 'udw', 'MISCREG_Y', None, 40),
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 82b1ed175..3ed2a9cc6 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -596,21 +596,36 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 
     // Be fast if we can!
     if (cacheValid &&  cacheState == tlbdata) {
-        if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
-            cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
-            (!write || cacheEntry[0]->pte.writable())) {
-                req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
-                              vaddr & cacheEntry[0]->pte.size()-1 );
-                return NoFault;
-        }
-        if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
-            cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
-            (!write || cacheEntry[1]->pte.writable())) {
-                req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
-                              vaddr & cacheEntry[1]->pte.size()-1 );
-                return NoFault;
-        }
-    }
+
+
+
+  if (cacheEntry[0]) {
+            TlbEntry *ce = cacheEntry[0];
+           Addr ce_va = ce->range.va;
+            if (cacheAsi[0] == asi &&
+                ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
+                (!write || ce->pte.writable())) {
+                    req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
+                    if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
+                        req->setFlags(req->getFlags() | UNCACHEABLE);
+                    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
+                    return NoFault;
+            } // if matched
+        } // if cache entry valid
+        if (cacheEntry[1]) {
+            TlbEntry *ce = cacheEntry[1];
+            Addr ce_va = ce->range.va;
+            if (cacheAsi[1] == asi &&
+                ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
+                (!write || ce->pte.writable())) {
+                    req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
+                    if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
+                        req->setFlags(req->getFlags() | UNCACHEABLE);
+                    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
+                    return NoFault;
+            } // if matched
+        } // if cache entry valid
+     }
 
     bool red = bits(tlbdata,1,1);
     bool priv = bits(tlbdata,2,2);
@@ -756,7 +771,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
     }
 
 
-    if (e->pte.sideffect())
+    if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
         req->setFlags(req->getFlags() | UNCACHEABLE);
 
     // cache translation date for next translation