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authorGabe Black <gblack@eecs.umich.edu>2006-08-21 22:41:57 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-08-21 22:41:57 -0400
commitdda9819d932a73ec1c9a07e4e10b3c2ed2a356bb (patch)
tree517632342b56d506aeb36ef7046be8085f4c1a22 /src/arch/sparc
parent3fa57c21f5ffc5148f4fa8b19fb67b6ee9bbf16f (diff)
downloadgem5-dda9819d932a73ec1c9a07e4e10b3c2ed2a356bb.tar.xz
Fix annulled unconditional branches
--HG-- extra : convert_revision : 698b0ce38c7a47306f97df2cc80cdae4a51b22c7
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/isa/decoder.isa49
-rw-r--r--src/arch/sparc/isa/formats/branch.isa10
2 files changed, 45 insertions, 14 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 3c5236661..0c8d77362 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -41,20 +41,45 @@ decode OP default Unknown::unknown()
0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
format BranchN
{
- 0x1: decode BPCC
+ 0x1: decode COND2
{
- 0x0: bpcci(19, {{
- if(passesCondition(Ccr<3:0>, COND2))
- NNPC = xc->readPC() + disp;
- else
- handle_annul
- }});
- 0x2: bpccx(19, {{
- if(passesCondition(Ccr<7:4>, COND2))
+ //Branch Always
+ 0x8: decode A
+ {
+ 0x0: b(19, {{
NNPC = xc->readPC() + disp;
- else
- handle_annul
- }});
+ }});
+ 0x1: b(19, {{
+ NPC = xc->readPC() + disp;
+ NNPC = NPC + 4;
+ }}, ',a');
+ }
+ //Branch Never
+ 0x0: decode A
+ {
+ 0x0: bn(19, {{
+ NNPC = NNPC;//Don't do anything
+ }});
+ 0x1: bn(19, {{
+ NPC = xc->readNextPC() + 4;
+ NNPC = NPC + 4;
+ }}, ',a');
+ }
+ default: decode BPCC
+ {
+ 0x0: bpcci(19, {{
+ if(passesCondition(Ccr<3:0>, COND2))
+ NNPC = xc->readPC() + disp;
+ else
+ handle_annul
+ }});
+ 0x2: bpccx(19, {{
+ if(passesCondition(Ccr<7:4>, COND2))
+ NNPC = xc->readPC() + disp;
+ else
+ handle_annul
+ }});
+ }
}
0x2: bicc(22, {{
if(passesCondition(Ccr<3:0>, COND2))
diff --git a/src/arch/sparc/isa/formats/branch.isa b/src/arch/sparc/isa/formats/branch.isa
index 8a3f05173..2c206354b 100644
--- a/src/arch/sparc/isa/formats/branch.isa
+++ b/src/arch/sparc/isa/formats/branch.isa
@@ -224,7 +224,6 @@ let {{
// Primary format for branch instructions:
def format Branch(code, *opt_flags) {{
- code = re.sub(r'handle_annul', handle_annul, code)
(usesImm, code, immCode,
rString, iString) = splitOutImm(code)
iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
@@ -246,7 +245,14 @@ def format Branch(code, *opt_flags) {{
def format BranchN(bits, code, *opt_flags) {{
code = re.sub(r'handle_annul', handle_annul, code)
codeBlk = CodeBlock(code)
- iop = InstObjParams(name, Name, "BranchNBits<%d>" % bits, codeBlk, opt_flags)
+ new_opt_flags = []
+ for flag in opt_flags:
+ if flag == ',a':
+ name += ',a'
+ Name += 'Annul'
+ else:
+ new_opt_flags += flag
+ iop = InstObjParams(name, Name, "BranchNBits<%d>" % bits, codeBlk, new_opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = BranchExecute.subst(iop)