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authorGabe Black <gblack@eecs.umich.edu>2007-03-13 16:13:21 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-03-13 16:13:21 +0000
commitce18d900a17cdda2cc041b51c56e6c84fb155331 (patch)
treed7be0cac19e550c93fc207e749ea80e1cf9a639e /src/arch/sparc
parent8edc9d79cee3edd6d16a8254a0180aaa242974c7 (diff)
downloadgem5-ce18d900a17cdda2cc041b51c56e6c84fb155331.tar.xz
Replaced makeExtMI with predecode.
Removed the getOpcode function from StaticInst which only made sense for Alpha. Started implementing the x86 predecoder. --HG-- extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/utility.hh14
1 files changed, 10 insertions, 4 deletions
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 64b91695e..4b662b5ac 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -48,9 +48,15 @@ namespace SparcISA
tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
}
- inline ExtMachInst
- makeExtMI(MachInst inst, ThreadContext * xc) {
- ExtMachInst emi = (MachInst) inst;
+ enum PredecodeResult {
+ MoreBytes = 1,
+ ExtMIReady = 2
+ };
+
+ inline unsigned int
+ predecode(ExtMachInst &emi, Addr currPC, MachInst inst,
+ ThreadContext * xc) {
+ emi = inst;
//The I bit, bit 13, is used to figure out where the ASI
//should come from. Use that in the ExtMachInst. This is
//slightly redundant, but it removes the need to put a condition
@@ -61,7 +67,7 @@ namespace SparcISA
else
emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
<< (sizeof(MachInst) * 8));
- return emi;
+ return MoreBytes | ExtMIReady;
}
inline bool isCallerSaveIntegerRegister(unsigned int reg) {