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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-08-15 05:08:30 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-08-15 05:08:30 -0400 |
| commit | cd6eb5396569bd2a3b16148f0d5277f7f4ee1391 (patch) | |
| tree | f587628bf43f6374ca351c295116b8b70fc90aee /src/arch/sparc | |
| parent | 74546aac0124a5ba09a0e6bfef18dc3e0b7509b8 (diff) | |
| parent | c9900f159e8d2fd7e32070e2cd0971caf917431d (diff) | |
| download | gem5-cd6eb5396569bd2a3b16148f0d5277f7f4ee1391.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
src/cpu/static_inst.hh:
SCCS merged
--HG--
extra : convert_revision : a4f6377dbd691ab58fe5f7958b983b092575f250
Diffstat (limited to 'src/arch/sparc')
| -rw-r--r-- | src/arch/sparc/ua2005.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc index b89d48663..6493ddfd5 100644 --- a/src/arch/sparc/ua2005.cc +++ b/src/arch/sparc/ua2005.cc @@ -37,7 +37,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, int64_t time; SparcSystem *sys; switch (miscReg) { - /** Full system only ASRs */ + /* Full system only ASRs */ case MISCREG_SOFTINT: if (isNonPriv()) return new PrivilegedOpcode; @@ -94,7 +94,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, sTickCompare.schedule(time * Clock::Int::ns); return NoFault; - /** Fullsystem only Priv registers. */ + /* Fullsystem only Priv registers. */ case MISCREG_PIL: if (FULL_SYSTEM) { setReg(miscReg, val); @@ -104,7 +104,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, } else panic("PIL not implemented for syscall emulation\n"); - /** Hyper privileged registers */ + /* Hyper privileged registers */ case MISCREG_HPSTATE: case MISCREG_HINTP: setReg(miscReg, val); @@ -147,7 +147,7 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc) { switch (miscReg) { - /** Privileged registers. */ + /* Privileged registers. */ case MISCREG_SOFTINT: if (isNonPriv()) { fault = new PrivilegedOpcode; @@ -177,7 +177,7 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc) return readReg(miscReg); - /** Hyper privileged registers */ + /* Hyper privileged registers */ case MISCREG_HPSTATE: case MISCREG_HINTP: return readReg(miscReg); |