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authorBrandon Potter <brandon.potter@amd.com>2018-05-04 17:55:24 -0400
committerAnthony Gutierrez <anthony.gutierrez@amd.com>2018-09-19 20:51:17 +0000
commit194d650536cb49c374efdb1fe0473b3eec5dea1e (patch)
tree38ca6c67b838f539d4e75dc05bd321f9e859091a /src/arch/sparc
parentc428c220fd351626e2ee0005dda696940261793b (diff)
downloadgem5-194d650536cb49c374efdb1fe0473b3eec5dea1e.tar.xz
syscall_emul: expand AuxVector class
The AuxVector class is responsible for holding Process data. The data that it holds is normally setup by an OS kernel in the process address space. The purpose behind doing this is to pass in information that the process will need for various reasons. (Check out the enum in the header file for an idea of what the AuxVector holds.) The AuxVector struct was changed into a class and encapsulation methods were added to protect access to the member variables. The host ISA may have a different endianness than the simulated ISA. Since data is passed between the process address space and the simulator for auxiliary vectors, we need to worry about maintaining endianness for the right context. Change-Id: I32c5ac4b679559886e1efeb4b5483b92dfc94af9 Reviewed-on: https://gem5-review.googlesource.com/12109 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/process.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index e4cd874bd..7dda6ed21 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -375,9 +375,9 @@ SparcProcess::argsInit(int pageSize)
// Copy the aux stuff
for (int x = 0; x < auxv.size(); x++) {
initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
- (uint8_t*)&(auxv[x].a_type), intSize);
+ (uint8_t*)&(auxv[x].getAuxType()), intSize);
initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
- (uint8_t*)&(auxv[x].a_val), intSize);
+ (uint8_t*)&(auxv[x].getAuxVal()), intSize);
}
// Write out the terminating zeroed auxilliary vector