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authorRekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com>2017-02-10 17:27:33 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-02-13 16:47:44 +0000
commit2d6afc6e2621fe67df09d4824ccd678a503b3517 (patch)
treec714bc1bc2af3b25b266849c515855b36f1e334e /src/arch/sparc
parente9f736738d61775cd3b739dbc9f85cbf4f4c135f (diff)
downloadgem5-2d6afc6e2621fe67df09d4824ccd678a503b3517.tar.xz
sim: Make Stats truly non-copy-constructible
The stats are silently non-copy constructible. Therefore, when someone copy-constructs any object with stats, asserts happen when registering the stats, as they were not constructed in the intended way. This patch solves that by explicitly deleting the copy constructor, trading an obscure run-time assert for a compile-time somehow more meaningful error meassage. This triggers some compilation errors as the FaultStats in the fault definitions of ARM and SPARC use brace-enclosed initialisations in which one of the elements derives from DataWrap, which is not copy-constructible anymore. To fix that, this patch also adds a constructor for the FaultVals in both ISAs. Change-Id: I340e203b9386609b32c66e3b8918a015afe415a4 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8082 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/faults.cc204
-rw-r--r--src/arch/sparc/faults.hh8
2 files changed, 109 insertions, 103 deletions
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 0f042b4ae..c5263cf58 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -51,227 +51,227 @@ namespace SparcISA
{
template<> SparcFaultBase::FaultVals
- SparcFault<PowerOnReset>::vals =
-{"power_on_reset", 0x001, 0, {H, H, H}, FaultStat()};
+ SparcFault<PowerOnReset>::vals
+("power_on_reset", 0x001, 0, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<WatchDogReset>::vals =
-{"watch_dog_reset", 0x002, 120, {H, H, H}, FaultStat()};
+ SparcFault<WatchDogReset>::vals
+("watch_dog_reset", 0x002, 120, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<ExternallyInitiatedReset>::vals =
-{"externally_initiated_reset", 0x003, 110, {H, H, H}, FaultStat()};
+ SparcFault<ExternallyInitiatedReset>::vals
+("externally_initiated_reset", 0x003, 110, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<SoftwareInitiatedReset>::vals =
-{"software_initiated_reset", 0x004, 130, {SH, SH, H}, FaultStat()};
+ SparcFault<SoftwareInitiatedReset>::vals
+("software_initiated_reset", 0x004, 130, {SH, SH, H});
template<> SparcFaultBase::FaultVals
- SparcFault<REDStateException>::vals =
-{"RED_state_exception", 0x005, 1, {H, H, H}, FaultStat()};
+ SparcFault<REDStateException>::vals
+("RED_state_exception", 0x005, 1, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<StoreError>::vals =
-{"store_error", 0x007, 201, {H, H, H}, FaultStat()};
+ SparcFault<StoreError>::vals
+("store_error", 0x007, 201, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<InstructionAccessException>::vals =
-{"instruction_access_exception", 0x008, 300, {H, H, H}, FaultStat()};
+ SparcFault<InstructionAccessException>::vals
+("instruction_access_exception", 0x008, 300, {H, H, H});
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
- SparcFault<InstructionAccessMMUMiss>::vals =
+ SparcFault<InstructionAccessMMUMiss>::vals
{"inst_mmu", 0x009, 2, {H, H, H}};*/
template<> SparcFaultBase::FaultVals
- SparcFault<InstructionAccessError>::vals =
-{"instruction_access_error", 0x00A, 400, {H, H, H}, FaultStat()};
+ SparcFault<InstructionAccessError>::vals
+("instruction_access_error", 0x00A, 400, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<IllegalInstruction>::vals =
-{"illegal_instruction", 0x010, 620, {H, H, H}, FaultStat()};
+ SparcFault<IllegalInstruction>::vals
+("illegal_instruction", 0x010, 620, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<PrivilegedOpcode>::vals =
-{"privileged_opcode", 0x011, 700, {P, SH, SH}, FaultStat()};
+ SparcFault<PrivilegedOpcode>::vals
+("privileged_opcode", 0x011, 700, {P, SH, SH});
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
- SparcFault<UnimplementedLDD>::vals =
+ SparcFault<UnimplementedLDD>::vals
{"unimp_ldd", 0x012, 6, {H, H, H}};*/
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
- SparcFault<UnimplementedSTD>::vals =
+ SparcFault<UnimplementedSTD>::vals
{"unimp_std", 0x013, 6, {H, H, H}};*/
template<> SparcFaultBase::FaultVals
- SparcFault<FpDisabled>::vals =
-{"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()};
+ SparcFault<FpDisabled>::vals
+("fp_disabled", 0x020, 800, {P, P, H});
/* SPARCv8 and SPARCv9 define just fp_disabled trap. SIMD is not contemplated
* as a separate part. Therefore, we use the same code and TT */
template<> SparcFaultBase::FaultVals
SparcFault<VecDisabled>::vals =
-{"fp_disabled", 0x020, 800, {P, P, H}, FaultStat()};
+{"fp_disabled", 0x020, 800, {P, P, H}};
template<> SparcFaultBase::FaultVals
- SparcFault<FpExceptionIEEE754>::vals =
-{"fp_exception_ieee_754", 0x021, 1110, {P, P, H}, FaultStat()};
+ SparcFault<FpExceptionIEEE754>::vals
+("fp_exception_ieee_754", 0x021, 1110, {P, P, H});
template<> SparcFaultBase::FaultVals
- SparcFault<FpExceptionOther>::vals =
-{"fp_exception_other", 0x022, 1110, {P, P, H}, FaultStat()};
+ SparcFault<FpExceptionOther>::vals
+("fp_exception_other", 0x022, 1110, {P, P, H});
template<> SparcFaultBase::FaultVals
- SparcFault<TagOverflow>::vals =
-{"tag_overflow", 0x023, 1400, {P, P, H}, FaultStat()};
+ SparcFault<TagOverflow>::vals
+("tag_overflow", 0x023, 1400, {P, P, H});
template<> SparcFaultBase::FaultVals
- SparcFault<CleanWindow>::vals =
-{"clean_window", 0x024, 1010, {P, P, H}, FaultStat()};
+ SparcFault<CleanWindow>::vals
+("clean_window", 0x024, 1010, {P, P, H});
template<> SparcFaultBase::FaultVals
- SparcFault<DivisionByZero>::vals =
-{"division_by_zero", 0x028, 1500, {P, P, H}, FaultStat()};
+ SparcFault<DivisionByZero>::vals
+("division_by_zero", 0x028, 1500, {P, P, H});
template<> SparcFaultBase::FaultVals
- SparcFault<InternalProcessorError>::vals =
-{"internal_processor_error", 0x029, 4, {H, H, H}, FaultStat()};
+ SparcFault<InternalProcessorError>::vals
+("internal_processor_error", 0x029, 4, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<InstructionInvalidTSBEntry>::vals =
-{"instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}, FaultStat()};
+ SparcFault<InstructionInvalidTSBEntry>::vals
+("instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH});
template<> SparcFaultBase::FaultVals
- SparcFault<DataInvalidTSBEntry>::vals =
-{"data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}, FaultStat()};
+ SparcFault<DataInvalidTSBEntry>::vals
+("data_invalid_tsb_entry", 0x02B, 1203, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<DataAccessException>::vals =
-{"data_access_exception", 0x030, 1201, {H, H, H}, FaultStat()};
+ SparcFault<DataAccessException>::vals
+("data_access_exception", 0x030, 1201, {H, H, H});
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
- SparcFault<DataAccessMMUMiss>::vals =
+ SparcFault<DataAccessMMUMiss>::vals
{"data_mmu", 0x031, 12, {H, H, H}};*/
template<> SparcFaultBase::FaultVals
- SparcFault<DataAccessError>::vals =
-{"data_access_error", 0x032, 1210, {H, H, H}, FaultStat()};
+ SparcFault<DataAccessError>::vals
+("data_access_error", 0x032, 1210, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<DataAccessProtection>::vals =
-{"data_access_protection", 0x033, 1207, {H, H, H}, FaultStat()};
+ SparcFault<DataAccessProtection>::vals
+("data_access_protection", 0x033, 1207, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<MemAddressNotAligned>::vals =
-{"mem_address_not_aligned", 0x034, 1020, {H, H, H}, FaultStat()};
+ SparcFault<MemAddressNotAligned>::vals
+("mem_address_not_aligned", 0x034, 1020, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<LDDFMemAddressNotAligned>::vals =
-{"LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}, FaultStat()};
+ SparcFault<LDDFMemAddressNotAligned>::vals
+("LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<STDFMemAddressNotAligned>::vals =
-{"STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}, FaultStat()};
+ SparcFault<STDFMemAddressNotAligned>::vals
+("STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<PrivilegedAction>::vals =
-{"privileged_action", 0x037, 1110, {H, H, SH}, FaultStat()};
+ SparcFault<PrivilegedAction>::vals
+("privileged_action", 0x037, 1110, {H, H, SH});
template<> SparcFaultBase::FaultVals
- SparcFault<LDQFMemAddressNotAligned>::vals =
-{"LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}, FaultStat()};
+ SparcFault<LDQFMemAddressNotAligned>::vals
+("LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<STQFMemAddressNotAligned>::vals =
-{"STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}, FaultStat()};
+ SparcFault<STQFMemAddressNotAligned>::vals
+("STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<InstructionRealTranslationMiss>::vals =
-{"instruction_real_translation_miss", 0x03E, 208, {H, H, SH}, FaultStat()};
+ SparcFault<InstructionRealTranslationMiss>::vals
+("instruction_real_translation_miss", 0x03E, 208, {H, H, SH});
template<> SparcFaultBase::FaultVals
- SparcFault<DataRealTranslationMiss>::vals =
-{"data_real_translation_miss", 0x03F, 1203, {H, H, H}, FaultStat()};
+ SparcFault<DataRealTranslationMiss>::vals
+("data_real_translation_miss", 0x03F, 1203, {H, H, H});
//XXX This trap is apparently dropped from ua2005
/*template<> SparcFaultBase::FaultVals
- SparcFault<AsyncDataError>::vals =
+ SparcFault<AsyncDataError>::vals
{"async_data", 0x040, 2, {H, H, H}};*/
template<> SparcFaultBase::FaultVals
- SparcFault<InterruptLevelN>::vals =
-{"interrupt_level_n", 0x040, 0, {P, P, SH}, FaultStat()};
+ SparcFault<InterruptLevelN>::vals
+("interrupt_level_n", 0x040, 0, {P, P, SH});
template<> SparcFaultBase::FaultVals
- SparcFault<HstickMatch>::vals =
-{"hstick_match", 0x05E, 1601, {H, H, H}, FaultStat()};
+ SparcFault<HstickMatch>::vals
+("hstick_match", 0x05E, 1601, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<TrapLevelZero>::vals =
-{"trap_level_zero", 0x05F, 202, {H, H, SH}, FaultStat()};
+ SparcFault<TrapLevelZero>::vals
+("trap_level_zero", 0x05F, 202, {H, H, SH});
template<> SparcFaultBase::FaultVals
- SparcFault<InterruptVector>::vals =
-{"interrupt_vector", 0x060, 2630, {H, H, H}, FaultStat()};
+ SparcFault<InterruptVector>::vals
+("interrupt_vector", 0x060, 2630, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<PAWatchpoint>::vals =
-{"PA_watchpoint", 0x061, 1209, {H, H, H}, FaultStat()};
+ SparcFault<PAWatchpoint>::vals
+("PA_watchpoint", 0x061, 1209, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<VAWatchpoint>::vals =
-{"VA_watchpoint", 0x062, 1120, {P, P, SH}, FaultStat()};
+ SparcFault<VAWatchpoint>::vals
+("VA_watchpoint", 0x062, 1120, {P, P, SH});
template<> SparcFaultBase::FaultVals
- SparcFault<FastInstructionAccessMMUMiss>::vals =
-{"fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}, FaultStat()};
+ SparcFault<FastInstructionAccessMMUMiss>::vals
+("fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH});
template<> SparcFaultBase::FaultVals
- SparcFault<FastDataAccessMMUMiss>::vals =
-{"fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}, FaultStat()};
+ SparcFault<FastDataAccessMMUMiss>::vals
+("fast_data_access_MMU_miss", 0x068, 1203, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<FastDataAccessProtection>::vals =
-{"fast_data_access_protection", 0x06C, 1207, {H, H, H}, FaultStat()};
+ SparcFault<FastDataAccessProtection>::vals
+("fast_data_access_protection", 0x06C, 1207, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<InstructionBreakpoint>::vals =
-{"instruction_break", 0x076, 610, {H, H, H}, FaultStat()};
+ SparcFault<InstructionBreakpoint>::vals
+("instruction_break", 0x076, 610, {H, H, H});
template<> SparcFaultBase::FaultVals
- SparcFault<CpuMondo>::vals =
-{"cpu_mondo", 0x07C, 1608, {P, P, SH}, FaultStat()};
+ SparcFault<CpuMondo>::vals
+("cpu_mondo", 0x07C, 1608, {P, P, SH});
template<> SparcFaultBase::FaultVals
- SparcFault<DevMondo>::vals =
-{"dev_mondo", 0x07D, 1611, {P, P, SH}, FaultStat()};
+ SparcFault<DevMondo>::vals
+("dev_mondo", 0x07D, 1611, {P, P, SH});
template<> SparcFaultBase::FaultVals
- SparcFault<ResumableError>::vals =
-{"resume_error", 0x07E, 3330, {P, P, SH}, FaultStat()};
+ SparcFault<ResumableError>::vals
+("resume_error", 0x07E, 3330, {P, P, SH});
template<> SparcFaultBase::FaultVals
- SparcFault<SpillNNormal>::vals =
-{"spill_n_normal", 0x080, 900, {P, P, H}, FaultStat()};
+ SparcFault<SpillNNormal>::vals
+("spill_n_normal", 0x080, 900, {P, P, H});
template<> SparcFaultBase::FaultVals
- SparcFault<SpillNOther>::vals =
-{"spill_n_other", 0x0A0, 900, {P, P, H}, FaultStat()};
+ SparcFault<SpillNOther>::vals
+("spill_n_other", 0x0A0, 900, {P, P, H});
template<> SparcFaultBase::FaultVals
- SparcFault<FillNNormal>::vals =
-{"fill_n_normal", 0x0C0, 900, {P, P, H}, FaultStat()};
+ SparcFault<FillNNormal>::vals
+("fill_n_normal", 0x0C0, 900, {P, P, H});
template<> SparcFaultBase::FaultVals
- SparcFault<FillNOther>::vals =
-{"fill_n_other", 0x0E0, 900, {P, P, H}, FaultStat()};
+ SparcFault<FillNOther>::vals
+("fill_n_other", 0x0E0, 900, {P, P, H});
template<> SparcFaultBase::FaultVals
- SparcFault<TrapInstruction>::vals =
-{"trap_instruction", 0x100, 1602, {P, P, H}, FaultStat()};
+ SparcFault<TrapInstruction>::vals
+("trap_instruction", 0x100, 1602, {P, P, H});
/**
* This causes the thread context to enter RED state. This causes the side
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 86f8c5b7d..88826bf61 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -57,13 +57,19 @@ class SparcFaultBase : public FaultBase
SH = -1,
ShouldntHappen = SH
};
+ using PrivilegeLevelSpec = std::array<PrivilegeLevel, NumLevels>;
struct FaultVals
{
const FaultName name;
const TrapType trapType;
const FaultPriority priority;
- const PrivilegeLevel nextPrivilegeLevel[NumLevels];
+ const PrivilegeLevelSpec nextPrivilegeLevel;
FaultStat count;
+ FaultVals(const FaultName& name_, const TrapType& trapType_,
+ const FaultPriority& priority_, const PrivilegeLevelSpec& il)
+ : name(name_), trapType(trapType_), priority(priority_),
+ nextPrivilegeLevel(il)
+ {}
};
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);