Merge zizzer:/bk/newmem

into  zeep.pool:/z/saidi/work/m5.suncc

--HG--
extra : convert_revision : 1706f6218abec7eb575dcff3ad4aef83894f64ab

8 files changed, 15 insertions, 9 deletions

diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 425ebc9d0..eae195a87 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -691,8 +691,8 @@ decode OP default Unknown::unknown()
                         Fsr &= ~(0x1F);
                     }});
                     0x0B: Trap::fabsq({{fault = new FpDisabled;}});
-                    0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
-                    0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
+                    0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
+                    0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
                     0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
                     0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
                     0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index a4c05387b..9805c7c0b 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -38,6 +38,7 @@ def template BasicExecPanic {{
         Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
         {
             panic("Execute method called when it shouldn't!");
+            M5_DUMMY_RETURN
         }
 }};
 
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 4f8ebebcc..9470fc55f 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -154,7 +154,7 @@ output decoder {{
         bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
                 const SymbolTable *symbab) const
         {
-            if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
+            if(!std::strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
             {
                 printMnemonic(os, "mov");
                 printSrcReg(os, 1);
@@ -168,7 +168,7 @@ output decoder {{
         bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
                 const SymbolTable *symbab) const
         {
-            if(!strcmp(mnemonic, "or"))
+            if(!std::strcmp(mnemonic, "or"))
             {
                 if(_numSrcRegs > 0 && _srcRegIdx[0] == 0)
                 {
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 0c112d481..5d90fbdd2 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -34,6 +34,7 @@
 //
 
 output header {{
+#include <cstring>
 #include <sstream>
 #include <iostream>
 
@@ -65,6 +66,7 @@ output exec {{
 #endif
 #include <limits>
 
+#include <cmath>
 #include "arch/sparc/asi.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 8aa8ea7f3..062cc8dd3 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -59,7 +59,7 @@ namespace SparcISA
     // These enumerate all the registers for dependence tracking.
     enum DependenceTags {
         FP_Base_DepTag = 33,
-        Ctrl_Base_DepTag = 97,
+        Ctrl_Base_DepTag = 97
     };
 
     // semantically meaningful register indices
diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc
index da83d86fc..800d47c15 100644
--- a/src/arch/sparc/system.cc
+++ b/src/arch/sparc/system.cc
@@ -195,6 +195,7 @@ bool
 SparcSystem::breakpoint()
 {
     panic("Need to implement");
+    M5_DUMMY_RETURN
 }
 
 void
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index bf57c894f..6ed6f59b6 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -28,6 +28,8 @@
  * Authors: Ali Saidi
  */
 
+#include <cstring>
+
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/miscregfile.hh"
 #include "arch/sparc/tlb.hh"
@@ -53,7 +55,7 @@ TLB::TLB(const std::string &name, int s)
         fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
 
     tlb = new TlbEntry[size];
-    memset(tlb, 0, sizeof(TlbEntry) * size);
+    std::memset(tlb, 0, sizeof(TlbEntry) * size);
 
     for (int x = 0; x < size; x++)
         freeList.push_back(&tlb[x]);
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 5c7fe343d..3c8bdcd01 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -50,7 +50,7 @@ namespace SparcISA
 
     inline ExtMachInst
     makeExtMI(MachInst inst, ThreadContext * xc) {
-        ExtMachInst emi = (unsigned MachInst) inst;
+        ExtMachInst emi = (MachInst) inst;
         //The I bit, bit 13, is used to figure out where the ASI
         //should come from. Use that in the ExtMachInst. This is
         //slightly redundant, but it removes the need to put a condition