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authorAli Saidi <saidi@eecs.umich.edu>2007-03-07 21:51:44 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-03-07 21:51:44 -0500
commit87fb0eb8de8bf66dfae5fc2d069cd17f420fc163 (patch)
treec7e3f1c653202f9d920eb740bb6dffa5ebd8df5e /src/arch/sparc
parent2f7a4e1d1b4ab44c5a1d97eaae6ff89fd100a0a9 (diff)
downloadgem5-87fb0eb8de8bf66dfae5fc2d069cd17f420fc163.tar.xz
I missed a couple of WithEffects, this should do it
--HG-- extra : convert_revision : 19fce78a19b27b7ccb5e3653a64b46e6d5292915
Diffstat (limited to 'src/arch/sparc')
-rw-r--r--src/arch/sparc/miscregfile.cc4
-rw-r--r--src/arch/sparc/miscregfile.hh5
-rw-r--r--src/arch/sparc/ua2005.cc5
3 files changed, 6 insertions, 8 deletions
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index e7b866e6f..20bc4ae5d 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -374,7 +374,7 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
case MISCREG_QUEUE_NRES_ERROR_TAIL:
#if FULL_SYSTEM
case MISCREG_HPSTATE:
- return readFSRegWithEffect(miscReg, tc);
+ return readFSReg(miscReg, tc);
#else
case MISCREG_HPSTATE:
//HPSTATE is special because because sometimes in privilege checks for instructions
@@ -682,7 +682,7 @@ void MiscRegFile::setReg(int miscReg,
case MISCREG_QUEUE_NRES_ERROR_TAIL:
#if FULL_SYSTEM
case MISCREG_HPSTATE:
- setFSRegWithEffect(miscReg, val, tc);
+ setFSReg(miscReg, val, tc);
return;
#else
case MISCREG_HPSTATE:
diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index cb46eb2aa..6063c21c8 100644
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -257,9 +257,8 @@ namespace SparcISA
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
#if FULL_SYSTEM
- void setFSRegWithEffect(int miscReg, const MiscReg &val,
- ThreadContext *tc);
- MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc);
+ void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
+ MiscReg readFSReg(int miscReg, ThreadContext * tc);
// Update interrupt state on softint or pil change
void checkSoftInt(ThreadContext *tc);
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 7a16dc352..6c8a987fe 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -59,8 +59,7 @@ MiscRegFile::checkSoftInt(ThreadContext *tc)
void
-MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
- ThreadContext *tc)
+MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
{
int64_t time;
switch (miscReg) {
@@ -196,7 +195,7 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
}
MiscReg
-MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
+MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
{
switch (miscReg) {
/* Privileged registers. */