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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-07-14 17:14:19 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-07-14 17:14:19 -0700 |
| commit | 4f7809d5e674384f58d3be6f4591afc0ceb2c37e (patch) | |
| tree | b776d1916615d67db85e1ccfc4374a52e09b8733 /src/arch/x86/SConscript | |
| parent | 92bb9242fb14db7ce3f78572ea428c8b3c06798a (diff) | |
| download | gem5-4f7809d5e674384f58d3be6f4591afc0ceb2c37e.tar.xz | |
Pull some hard coded base classes out of the isa description.
--HG--
rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa
extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c
Diffstat (limited to 'src/arch/x86/SConscript')
| -rw-r--r-- | src/arch/x86/SConscript | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 6de243c9c..e8f8059ce 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -87,6 +87,9 @@ Import('*') if env['TARGET_ISA'] == 'x86': Source('emulenv.cc') Source('floatregfile.cc') + Source('insts/microldstop.cc') + Source('insts/microregop.cc') + Source('insts/static_inst.cc') Source('intregfile.cc') Source('miscregfile.cc') Source('predecoder.cc') |