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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 15:31:28 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-10-12 15:31:28 -0700 |
| commit | a76c4b8ca101c0c89659a536da6271d4116850de (patch) | |
| tree | 3dc57ad774f0bb768c58b50540a6b08a7530aec8 /src/arch/x86/SConscript | |
| parent | d0a43ce2b29da1640248a756dcd07f0f28561df0 (diff) | |
| download | gem5-a76c4b8ca101c0c89659a536da6271d4116850de.tar.xz | |
X86: Implement CPUID with a magical function instead of microcode.
Diffstat (limited to 'src/arch/x86/SConscript')
| -rw-r--r-- | src/arch/x86/SConscript | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index c1a1b9ba3..cd2445c7e 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -86,6 +86,7 @@ Import('*') if env['TARGET_ISA'] == 'x86': + Source('cpuid.cc') Source('emulenv.cc') Source('floatregfile.cc') Source('faults.cc') @@ -173,7 +174,6 @@ if env['TARGET_ISA'] == 'x86': 'general_purpose/load_segment_registers.py', 'general_purpose/logical.py', 'general_purpose/no_operation.py', - 'general_purpose/processor_information.py', 'general_purpose/rotate_and_shift/__init__.py', 'general_purpose/rotate_and_shift/rotate.py', 'general_purpose/rotate_and_shift/shift.py', |