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| author | Derek Hower <drh5@cs.wisc.edu> | 2009-07-20 09:41:28 -0500 |
|---|---|---|
| committer | Derek Hower <drh5@cs.wisc.edu> | 2009-07-20 09:41:28 -0500 |
| commit | 225de2eaff57bdf27d367531f25a654e4cd06fe6 (patch) | |
| tree | 641e3e3e268359438d9dfcd07f0025d520dc870f /src/arch/x86/SConscript | |
| parent | e59d0e3e89f46f35065ab318c8578941203cc657 (diff) | |
| parent | 3e8e813218e7779a41bc12caae33db5e239506c9 (diff) | |
| download | gem5-225de2eaff57bdf27d367531f25a654e4cd06fe6.tar.xz | |
merge
Diffstat (limited to 'src/arch/x86/SConscript')
| -rw-r--r-- | src/arch/x86/SConscript | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 96af0767c..3d1f6f8e3 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -95,6 +95,7 @@ if env['TARGET_ISA'] == 'x86': Source('insts/microregop.cc') Source('insts/static_inst.cc') Source('isa.cc') + Source('nativetrace.cc') Source('pagetable.cc') Source('predecoder.cc') Source('predecoder_tables.cc') @@ -102,6 +103,8 @@ if env['TARGET_ISA'] == 'x86': Source('tlb.cc') Source('utility.cc') + SimObject('X86NativeTrace.py') + SimObject('X86TLB.py') TraceFlag('Predecoder', "Predecoder debug output") TraceFlag('X86', "Generic X86 ISA debugging") |