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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-10-12 16:37:55 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-10-12 16:37:55 -0700 |
| commit | 9498e536c0231b808669f2bacb4c0628d1ec309a (patch) | |
| tree | 13edd1623e87077269a03b10a37a66bf61f4f969 /src/arch/x86/SConscript | |
| parent | 8b35bd6fe79ce069428431a4edbe43b8373f7e87 (diff) | |
| download | gem5-9498e536c0231b808669f2bacb4c0628d1ec309a.tar.xz | |
X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.
--HG--
extra : convert_revision : ff893eb569313d8aecbfffb47bcbd1c2d65cd393
Diffstat (limited to 'src/arch/x86/SConscript')
| -rw-r--r-- | src/arch/x86/SConscript | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index 6d7984147..6d65fbb57 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -179,6 +179,7 @@ if env['TARGET_ISA'] == 'x86': 'general_purpose/system_calls.py', 'system/__init__.py', 'system/undefined_operation.py', + 'system/msrs.py', 'simd128/__init__.py', 'simd128/integer/__init__.py', 'simd128/integer/data_transfer/__init__.py', |