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authorDylan Johnson <Dylan.Johnson@ARM.com>2016-08-02 10:38:01 +0100
committerDylan Johnson <Dylan.Johnson@ARM.com>2016-08-02 10:38:01 +0100
commit4fbf40daab480ae02b75a75e0dd5f56ce38386d2 (patch)
treeda3988cf1979f5b7b655661ede690cc0b23aa01d /src/arch/x86/X86LocalApic.py
parente727a0eeaa5f2d46921c8496d77623a9704d40b6 (diff)
downloadgem5-4fbf40daab480ae02b75a75e0dd5f56ce38386d2.tar.xz
arm: invalidate TLB miscreg cache on modification of HSCTLR
Change-Id: I5212c91c56435fe008950ed99feacc6921609226
Diffstat (limited to 'src/arch/x86/X86LocalApic.py')
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