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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-10-13 02:22:23 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-10-13 02:22:23 -0700 |
| commit | 8adc6781bf5741cca9a27e9e2c523b4def5a3bc3 (patch) | |
| tree | 4beebe8b1f71fe8847045bd6e57182c6ab4e1ec8 /src/arch/x86/X86TLB.py | |
| parent | 4b2e5ebeada762e88ad97397b8db3ebf4658b70f (diff) | |
| download | gem5-8adc6781bf5741cca9a27e9e2c523b4def5a3bc3.tar.xz | |
X86: Turn on the page table walker in SE mode.
Diffstat (limited to 'src/arch/x86/X86TLB.py')
| -rw-r--r-- | src/arch/x86/X86TLB.py | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index ae9bfd353..7f2fcd358 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -35,24 +35,21 @@ # # Authors: Gabe Black -from m5.defines import buildEnv from m5.params import * from m5.proxy import * from BaseTLB import BaseTLB from MemObject import MemObject -if buildEnv['FULL_SYSTEM']: - class X86PagetableWalker(MemObject): - type = 'X86PagetableWalker' - cxx_class = 'X86ISA::Walker' - port = Port("Port for the hardware table walker") - system = Param.System(Parent.any, "system object") +class X86PagetableWalker(MemObject): + type = 'X86PagetableWalker' + cxx_class = 'X86ISA::Walker' + port = Port("Port for the hardware table walker") + system = Param.System(Parent.any, "system object") class X86TLB(BaseTLB): type = 'X86TLB' cxx_class = 'X86ISA::TLB' size = Param.Int(64, "TLB size") - if buildEnv['FULL_SYSTEM']: - walker = Param.X86PagetableWalker(\ - X86PagetableWalker(), "page table walker") + walker = Param.X86PagetableWalker(\ + X86PagetableWalker(), "page table walker") |