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authorAndreas Sandberg <Andreas.Sandberg@arm.com>2012-11-02 11:32:01 -0500
committerAndreas Sandberg <Andreas.Sandberg@arm.com>2012-11-02 11:32:01 -0500
commitc0ab52799ca4ebd0a51363cfedd0658e6d79b842 (patch)
treeafdf65e4593c64bbc1d5b511aacbaf0fa4b558ad /src/arch/x86/X86TLB.py
parent044a6525876efc61838dffa89ac52425d510b754 (diff)
downloadgem5-c0ab52799ca4ebd0a51363cfedd0658e6d79b842.tar.xz
sim: Include object header files in SWIG interfaces
When casting objects in the generated SWIG interfaces, SWIG uses classical C-style casts ( (Foo *)bar; ). In some cases, this can degenerate into the equivalent of a reinterpret_cast (mainly if only a forward declaration of the type is available). This usually works for most compilers, but it is known to break if multiple inheritance is used anywhere in the object hierarchy. This patch introduces the cxx_header attribute to Python SimObject definitions, which should be used to specify a header to include in the SWIG interface. The header should include the declaration of the wrapped object. We currently don't enforce header the use of the header attribute, but a warning will be generated for objects that do not use it.
Diffstat (limited to 'src/arch/x86/X86TLB.py')
-rw-r--r--src/arch/x86/X86TLB.py2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 334d2a0cf..a08dbb138 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -44,12 +44,14 @@ from MemObject import MemObject
class X86PagetableWalker(MemObject):
type = 'X86PagetableWalker'
cxx_class = 'X86ISA::Walker'
+ cxx_header = 'arch/x86/pagetable_walker.hh'
port = MasterPort("Port for the hardware table walker")
system = Param.System(Parent.any, "system object")
class X86TLB(BaseTLB):
type = 'X86TLB'
cxx_class = 'X86ISA::TLB'
+ cxx_header = 'arch/x86/tlb.hh'
size = Param.Int(64, "TLB size")
walker = Param.X86PagetableWalker(\
X86PagetableWalker(), "page table walker")