diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2008-10-10 23:47:42 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-10-10 23:47:42 -0700 |
| commit | 8c5dfa453296c5a87a46c409f68e0ef50ebfceb6 (patch) | |
| tree | 18d96ff626b3fbaf17e6da31f74be73f4ff805e9 /src/arch/x86/X86TLB.py | |
| parent | 3d1734ec29a0572a2c0fe403d737adbd9756c993 (diff) | |
| download | gem5-8c5dfa453296c5a87a46c409f68e0ef50ebfceb6.tar.xz | |
TLB: Make all tlbs derive from a common base class in both python and C++.
Diffstat (limited to 'src/arch/x86/X86TLB.py')
| -rw-r--r-- | src/arch/x86/X86TLB.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index c20566efb..d5ae95372 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -54,10 +54,10 @@ # Authors: Gabe Black from MemObject import MemObject -from m5.SimObject import SimObject from m5.params import * from m5.proxy import * from m5 import build_env +from BaseTLB import BaseTLB if build_env['FULL_SYSTEM']: class X86PagetableWalker(MemObject): @@ -66,7 +66,7 @@ if build_env['FULL_SYSTEM']: port = Port("Port for the hardware table walker") system = Param.System(Parent.any, "system object") -class X86TLB(SimObject): +class X86TLB(BaseTLB): type = 'X86TLB' abstract = True size = Param.Int("TLB size") |