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author | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 18:06:57 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 18:06:57 -0800 |
commit | 1048b548fabfb7af2113f226f2151d3eb0e63289 (patch) | |
tree | d68b47ad4f335ade253f5ae87a158c6209d6ec20 /src/arch/x86/X86TLB.py | |
parent | 6095dceb0c34cf79ecbd799ab4b2cbe7b7c8629a (diff) | |
download | gem5-1048b548fabfb7af2113f226f2151d3eb0e63289.tar.xz |
X86: Separate out the page table walker into it's own cc and hh.
--HG--
extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042
Diffstat (limited to 'src/arch/x86/X86TLB.py')
-rw-r--r-- | src/arch/x86/X86TLB.py | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index 5c174be59..dc080f37e 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -54,15 +54,28 @@ # Authors: Gabe Black from MemObject import MemObject +from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from m5 import build_env -class X86TLB(MemObject): +if build_env['FULL_SYSTEM']: + class X86PagetableWalker(MemObject): + type = 'X86PagetableWalker' + cxx_namespace = 'X86ISA' + cxx_class = 'Walker' + port = Port("Port for the hardware table walker") + system = Param.System(Parent.any, "system object") + +class X86TLB(SimObject): type = 'X86TLB' + cxx_namespace = 'X86ISA' + cxx_class = 'TLB' abstract = True size = Param.Int("TLB size") - walker_port = Port("Port for the hardware table walker") - system = Param.System(Parent.any, "system object") + if build_env['FULL_SYSTEM']: + walker = Param.X86PagetableWalker(\ + X86PagetableWalker(), "page table walker") class X86DTB(X86TLB): type = 'X86DTB' |