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| author | Gedare Bloom <gedare@rtems.org> | 2013-05-21 11:40:11 -0500 |
|---|---|---|
| committer | Gedare Bloom <gedare@rtems.org> | 2013-05-21 11:40:11 -0500 |
| commit | 22b60c57e697289baa205f11b164f356363c2bee (patch) | |
| tree | 4206562aae3cdb8b82a3ec8e873f15444502c678 /src/arch/x86/X86TLB.py | |
| parent | 30fe807316ebc4b6c37ca522b3cfd6c592ca9003 (diff) | |
| download | gem5-22b60c57e697289baa205f11b164f356363c2bee.tar.xz | |
x86: Squash outstanding walks when instructions are squashed.
This is the x86 version of the ARM changeset baa17ba80e06. In case an
instruction has been squashed by the o3 cpu, this patch allows page
table walker to avoid carrying out a pending translation that the
instruction requested for.
Diffstat (limited to 'src/arch/x86/X86TLB.py')
| -rw-r--r-- | src/arch/x86/X86TLB.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index a08dbb138..b652118ce 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -47,6 +47,8 @@ class X86PagetableWalker(MemObject): cxx_header = 'arch/x86/pagetable_walker.hh' port = MasterPort("Port for the hardware table walker") system = Param.System(Parent.any, "system object") + num_squash_per_cycle = Param.Unsigned(4, + "Number of outstanding walks that can be squashed per cycle") class X86TLB(BaseTLB): type = 'X86TLB' |