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authorGabe Black <gblack@eecs.umich.edu>2009-04-08 22:21:27 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-04-08 22:21:27 -0700
commit7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 (patch)
tree4c212f665de2628eac6f84d389de7a79b6d0b933 /src/arch/x86/X86TLB.py
parent08043c777f1f05f5e14581950013461f328965be (diff)
downloadgem5-7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60.tar.xz
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
Diffstat (limited to 'src/arch/x86/X86TLB.py')
-rw-r--r--src/arch/x86/X86TLB.py14
1 files changed, 2 insertions, 12 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index d5ae95372..15b03fd33 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -68,18 +68,8 @@ if build_env['FULL_SYSTEM']:
class X86TLB(BaseTLB):
type = 'X86TLB'
- abstract = True
- size = Param.Int("TLB size")
+ cxx_class = 'X86ISA::TLB'
+ size = Param.Int(64, "TLB size")
if build_env['FULL_SYSTEM']:
walker = Param.X86PagetableWalker(\
X86PagetableWalker(), "page table walker")
-
-class X86DTB(X86TLB):
- type = 'X86DTB'
- cxx_class = 'X86ISA::DTB'
- size = 64
-
-class X86ITB(X86TLB):
- type = 'X86ITB'
- cxx_class = 'X86ISA::ITB'
- size = 64