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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:24 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:24 -0800 |
| commit | f17f3d20be08d25f176138691a29897df54e5cc0 (patch) | |
| tree | b10a30a948462b94c5f1b9001fb7dc314d32cf32 /src/arch/x86/X86TLB.py | |
| parent | 7a39457d7ff5fd80484061a4ff7006921899b229 (diff) | |
| download | gem5-f17f3d20be08d25f176138691a29897df54e5cc0.tar.xz | |
X86: Implement a page table walker.
--HG--
extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec
Diffstat (limited to 'src/arch/x86/X86TLB.py')
| -rw-r--r-- | src/arch/x86/X86TLB.py | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py index ce4db4f4c..2d562ba9a 100644 --- a/src/arch/x86/X86TLB.py +++ b/src/arch/x86/X86TLB.py @@ -53,12 +53,15 @@ # # Authors: Gabe Black -from m5.SimObject import SimObject +from MemObject import MemObject from m5.params import * -class X86TLB(SimObject): + +class X86TLB(MemObject): type = 'X86TLB' abstract = True size = Param.Int("TLB size") + walker_port = Port("Port for the hardware table walker") + system = Param.System(Parent.any, "system object") class X86DTB(X86TLB): type = 'X86DTB' |