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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-17 12:55:08 -0600 |
commit | f85286b3debf4a4a94d3b959e5bb880be81bd692 (patch) | |
tree | 56a6be55a52d6cc6bb7e5d92fdcb25c79ad7d196 /src/arch/x86/bios/intelmp.hh | |
parent | 06c39a154c4dc8fedcf9fbf77bbcf26f176c469c (diff) | |
download | gem5-f85286b3debf4a4a94d3b959e5bb880be81bd692.tar.xz |
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable
all ports in the system to correspond to a structural entity. This has
the advantage of accessing memory through the normal memory subsystem
and thus allowing any constellation of distributed memories, address
maps, etc. Most accesses are done through the "system port" that is
used for loading binaries, debugging etc. For the entities that belong
to the CPU, e.g. threads and thread contexts, they wrap the CPU data
port in a port proxy.
The following replacements are made:
FunctionalPort > PortProxy
TranslatingPort > SETranslatingPortProxy
VirtualPort > FSTranslatingPortProxy
--HG--
rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc
rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh
rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc
rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'src/arch/x86/bios/intelmp.hh')
-rw-r--r-- | src/arch/x86/bios/intelmp.hh | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/arch/x86/bios/intelmp.hh b/src/arch/x86/bios/intelmp.hh index 117466b48..0ddb62b8d 100644 --- a/src/arch/x86/bios/intelmp.hh +++ b/src/arch/x86/bios/intelmp.hh @@ -51,7 +51,7 @@ #include "enums/X86IntelMPTriggerMode.hh" #include "sim/sim_object.hh" -class FunctionalPort; +class PortProxy; // Config entry types class X86IntelMPBaseConfigEntryParams; @@ -93,7 +93,7 @@ class FloatingPointer : public SimObject public: - Addr writeOut(FunctionalPort * port, Addr addr); + Addr writeOut(PortProxy* proxy, Addr addr); Addr getTableAddr() { @@ -117,7 +117,7 @@ class BaseConfigEntry : public SimObject public: - virtual Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); + virtual Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); BaseConfigEntry(Params * p, uint8_t _type); }; @@ -132,7 +132,7 @@ class ExtConfigEntry : public SimObject public: - virtual Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); + virtual Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); ExtConfigEntry(Params * p, uint8_t _type, uint8_t _length); }; @@ -155,7 +155,7 @@ class ConfigTable : public SimObject std::vector<ExtConfigEntry *> extEntries; public: - Addr writeOut(FunctionalPort * port, Addr addr); + Addr writeOut(PortProxy* proxy, Addr addr); ConfigTable(Params * p); }; @@ -172,7 +172,7 @@ class Processor : public BaseConfigEntry uint32_t featureFlags; public: - Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); + Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); Processor(Params * p); }; @@ -186,7 +186,7 @@ class Bus : public BaseConfigEntry std::string busType; public: - Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); + Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); Bus(Params * p); }; @@ -202,7 +202,7 @@ class IOAPIC : public BaseConfigEntry uint32_t address; public: - Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); + Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); IOAPIC(Params * p); }; @@ -221,7 +221,7 @@ class IntAssignment : public BaseConfigEntry uint8_t destApicIntIn; public: - Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); + Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); IntAssignment(X86IntelMPBaseConfigEntryParams * p, Enums::X86IntelMPInterruptType _interruptType, @@ -269,7 +269,7 @@ class AddrSpaceMapping : public ExtConfigEntry uint64_t addrLength; public: - Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); + Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); AddrSpaceMapping(Params * p); }; @@ -284,7 +284,7 @@ class BusHierarchy : public ExtConfigEntry uint8_t parentBus; public: - Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); + Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); BusHierarchy(Params * p); }; @@ -299,7 +299,7 @@ class CompatAddrSpaceMod : public ExtConfigEntry uint32_t rangeList; public: - Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum); + Addr writeOut(PortProxy* proxy, Addr addr, uint8_t &checkSum); CompatAddrSpaceMod(Params * p); }; |