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authorGabe Black <gblack@eecs.umich.edu>2007-08-04 20:12:54 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-04 20:12:54 -0700
commite410a925df8d37f386c97dc7cdd9a78347ce4700 (patch)
treeb4102987453b1303051dfeea61aa1a45c2e5e75f /src/arch/x86/emulenv.cc
parentced6cbcccf4540358093f060dad4d59ad6557d6a (diff)
downloadgem5-e410a925df8d37f386c97dc7cdd9a78347ce4700.tar.xz
X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment base addresses. Also fix some microcode and add sib and riprel "keywords" to the x86 specialization of the microassembler. --HG-- extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
Diffstat (limited to 'src/arch/x86/emulenv.cc')
-rw-r--r--src/arch/x86/emulenv.cc13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/arch/x86/emulenv.cc b/src/arch/x86/emulenv.cc
index 28282dc7a..31b705d79 100644
--- a/src/arch/x86/emulenv.cc
+++ b/src/arch/x86/emulenv.cc
@@ -88,5 +88,18 @@ void EmulEnv::doModRM(const ExtMachInst & machInst)
}
}
}
+ //Figure out what segment to use. This won't be entirely accurate since
+ //the presence of a displacement is supposed to make the instruction
+ //default to the data segment.
+ if (base != INTREG_RBP && base != INTREG_RSP ||
+ 0/*Has an immediate offset*/) {
+ seg = SEGMENT_REG_DS;
+ //Handle any segment override that might have been in the instruction
+ int segFromInst = machInst.legacy.seg;
+ if (segFromInst)
+ seg = (SegmentRegIndex)(segFromInst - 1);
+ } else {
+ seg = SEGMENT_REG_SS;
+ }
}