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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:17:59 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:17:59 -0800 |
| commit | 1cedc748d413513c1bb98a454cc035f35b30f0f9 (patch) | |
| tree | 7d03b1f784d5332327821e5d11a024b7a03b44eb /src/arch/x86/faults.cc | |
| parent | eec3f49a57aca83e492e72b9cf55a8c6c6ebae73 (diff) | |
| download | gem5-1cedc748d413513c1bb98a454cc035f35b30f0f9.tar.xz | |
X86: Add a trace flag for tracing faults.
Diffstat (limited to 'src/arch/x86/faults.cc')
| -rw-r--r-- | src/arch/x86/faults.cc | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc index 964eb0a7f..b81400cc3 100644 --- a/src/arch/x86/faults.cc +++ b/src/arch/x86/faults.cc @@ -103,6 +103,8 @@ namespace X86ISA #if FULL_SYSTEM void X86FaultBase::invoke(ThreadContext * tc) { + Addr pc = tc->readPC(); + DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe()); using namespace X86ISAInst::RomLabels; HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); MicroPC entry; @@ -116,7 +118,7 @@ namespace X86ISA entry = extern_label_legacyModeInterrupt; } tc->setIntReg(INTREG_MICRO(1), vector); - tc->setIntReg(INTREG_MICRO(7), tc->readPC()); + tc->setIntReg(INTREG_MICRO(7), pc); if (errorCode != (uint64_t)(-1)) { if (m5reg.mode == LongMode) { entry = extern_label_longModeInterruptWithError; @@ -132,6 +134,18 @@ namespace X86ISA tc->setMicroPC(romMicroPC(entry)); tc->setNextMicroPC(romMicroPC(entry) + 1); } + + std::string + X86FaultBase::describe() const + { + std::stringstream ss; + ccprintf(ss, "%s", mnemonic()); + if (errorCode != (uint64_t)(-1)) { + ccprintf(ss, "(%#x)", errorCode); + } + + return ss.str(); + } void X86Trap::invoke(ThreadContext * tc) { @@ -163,6 +177,14 @@ namespace X86ISA } } + std::string + PageFault::describe() const + { + std::stringstream ss; + ccprintf(ss, "%s at %#x", X86FaultBase::describe(), addr); + return ss.str(); + } + #endif } // namespace X86ISA |