X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging.

--HG--
extra : convert_revision : 6072f7d9eecbaa066d39d6da7f0180ea4a2615af

1 files changed, 171 insertions, 0 deletions

diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
new file mode 100644
index 000000000..124dcf41e
--- /dev/null
+++ b/src/arch/x86/faults.cc
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+/*
+ * Copyright (c) 2003-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use.  Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ *     Director of Intellectual Property Licensing
+ *     Office of Strategy and Technology
+ *     Hewlett-Packard Company
+ *     1501 Page Mill Road
+ *     Palo Alto, California  94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.  Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.  Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.  No right of
+ * sublicense is granted herewith.  Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses.  Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/faults.hh"
+#include "base/trace.hh"
+#include "config/full_system.hh"
+#include "cpu/thread_context.hh"
+#if !FULL_SYSTEM
+#include "arch/x86/isa_traits.hh"
+#include "mem/page_table.hh"
+#include "sim/process.hh"
+#endif
+
+namespace X86ISA
+{
+#if FULL_SYSTEM
+    void X86Trap::invoke(TheeadContext * tc)
+    {
+        panic("X86 faults are not implemented!");
+    }
+
+    void X86Abort::invoke(TheeadContext * tc)
+    {
+        panic("X86 faults are not implemented!");
+    }
+
+    void X86Interrupt::invoke(TheeadContext * tc)
+    {
+        panic("X86 faults are not implemented!");
+    }
+#else // !FULL_SYSTEM
+    void FakeITLBFault::invoke(ThreadContext * tc)
+    {
+        DPRINTF(TLB, "Invoking an ITLB fault for address %#x at pc %#x.\n",
+                vaddr, tc->readPC());
+        Process *p = tc->getProcessPtr();
+        Addr paddr;
+        bool success = p->pTable->translate(vaddr, paddr);
+        if(!success) {
+            panic("Tried to execute unmapped address %#x.\n", vaddr);
+        } else {
+            TlbEntry entry;
+            entry.pageStart = p->pTable->pageAlign(paddr);
+            entry.writeable = false;
+            entry.user = true;
+            entry.uncacheable = false;
+            entry.global = false;
+            entry.patBit = 0;
+            entry.noExec = false;
+            entry.size = PageBytes;
+            Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+            DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
+            tc->getITBPtr()->insert(alignedVaddr, entry);
+        }
+    }
+
+    void FakeDTLBFault::invoke(ThreadContext * tc)
+    {
+        DPRINTF(TLB, "Invoking an DTLB fault for address %#x at pc %#x.\n",
+                vaddr, tc->readPC());
+        Process *p = tc->getProcessPtr();
+        Addr paddr;
+        bool success = p->pTable->translate(vaddr, paddr);
+        if(!success) {
+            p->checkAndAllocNextPage(vaddr);
+            success = p->pTable->translate(vaddr, paddr);
+        }
+        if(!success) {
+            panic("Tried to access unmapped address %#x.\n", vaddr);
+        } else {
+            TlbEntry entry;
+            entry.pageStart = p->pTable->pageAlign(paddr);
+            entry.writeable = true;
+            entry.user = true;
+            entry.uncacheable = false;
+            entry.global = false;
+            entry.patBit = 0;
+            entry.noExec = true;
+            entry.size = PageBytes;
+            Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+            DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, entry.pageStart);
+            tc->getDTBPtr()->insert(alignedVaddr, entry);
+        }
+    }
+#endif
+} // namespace X86ISA
+