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author | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:16:21 -0800 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-02-25 10:16:21 -0800 |
commit | 40fdba2454c219902db7ad1abd28593de8611c2b (patch) | |
tree | 79369b7e2d1caae9f0accd45e6f9a0f53c1002f2 /src/arch/x86/faults.hh | |
parent | 6ed47e94644f854baa33d1e9f367cc9eebd99abf (diff) | |
download | gem5-40fdba2454c219902db7ad1abd28593de8611c2b.tar.xz |
X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults.
Diffstat (limited to 'src/arch/x86/faults.hh')
-rw-r--r-- | src/arch/x86/faults.hh | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh index ae4314434..3753e60e5 100644 --- a/src/arch/x86/faults.hh +++ b/src/arch/x86/faults.hh @@ -422,38 +422,6 @@ namespace X86ISA return true; } }; - - // These faults aren't part of the ISA definition. They trigger filling - // the tlb on a miss and are to take the place of a hardware table walker. - class FakeITLBFault : public X86Fault - { - protected: - Addr vaddr; - bool write; - bool execute; - public: - FakeITLBFault(Addr _vaddr, bool _write, bool _execute) : - X86Fault("fake instruction tlb fault", "itlb", 0), - vaddr(_vaddr), write(_write), execute(_execute) - {} - - void invoke(ThreadContext * tc); - }; - - class FakeDTLBFault : public X86Fault - { - protected: - Addr vaddr; - bool write; - bool execute; - public: - FakeDTLBFault(Addr _vaddr, bool _write, bool _execute) : - X86Fault("fake data tlb fault", "dtlb", 0), - vaddr(_vaddr), write(_write), execute(_execute) - {} - - void invoke(ThreadContext * tc); - }; }; #endif // __ARCH_X86_FAULTS_HH__ |