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authorGabe Black <gblack@eecs.umich.edu>2007-11-12 14:38:31 -0800
committerGabe Black <gblack@eecs.umich.edu>2007-11-12 14:38:31 -0800
commitfce45baf178b43c2ea1476967fba3766e9b2ea9d (patch)
tree1aa3ba357950f9a18e2d7a7e6fd4be8c8d0e5d91 /src/arch/x86/faults.hh
parentf17f3d20be08d25f176138691a29897df54e5cc0 (diff)
downloadgem5-fce45baf178b43c2ea1476967fba3766e9b2ea9d.tar.xz
X86: Work on the page table walker, TLB, and related faults.
--HG-- extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f
Diffstat (limited to 'src/arch/x86/faults.hh')
-rw-r--r--src/arch/x86/faults.hh16
1 files changed, 0 insertions, 16 deletions
diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index 5a573754a..78a55d0e1 100644
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -369,44 +369,28 @@ namespace X86ISA
// the tlb on a miss and are to take the place of a hardware table walker.
class FakeITLBFault : public X86Fault
{
-#if !FULL_SYSTEM
protected:
Addr vaddr;
public:
FakeITLBFault(Addr _vaddr) :
X86Fault("fake instruction tlb fault", "itlb"),
vaddr(_vaddr)
-#else
- public:
- FakeITLBFault() :
- X86Fault("fake instruction tlb fault", "itlb")
-#endif
{}
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc);
-#endif
};
class FakeDTLBFault : public X86Fault
{
-#if !FULL_SYSTEM
protected:
Addr vaddr;
public:
FakeDTLBFault(Addr _vaddr) :
X86Fault("fake data tlb fault", "dtlb"),
vaddr(_vaddr)
-#else
- public:
- FakeDTLBFault() :
- X86Fault("fake data tlb fault", "dtlb")
-#endif
{}
-#if !FULL_SYSTEM
void invoke(ThreadContext * tc);
-#endif
};
};