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authorGabe Black <gblack@eecs.umich.edu>2009-02-25 10:22:17 -0800
committerGabe Black <gblack@eecs.umich.edu>2009-02-25 10:22:17 -0800
commit4633677145225a76ee3826ef97a24b1e427f61f8 (patch)
tree0165533bf8760a7f44b71f5ad5f9c1cd9fb301a9 /src/arch/x86/floatregfile.cc
parent44d5351071d3f9ec80f2fab7876d757cfbd5bacf (diff)
downloadgem5-4633677145225a76ee3826ef97a24b1e427f61f8.tar.xz
ISA: Set up common trace flags for tracing registers.
Diffstat (limited to 'src/arch/x86/floatregfile.cc')
-rw-r--r--src/arch/x86/floatregfile.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/x86/floatregfile.cc b/src/arch/x86/floatregfile.cc
index 1c49ea9c6..da5372c69 100644
--- a/src/arch/x86/floatregfile.cc
+++ b/src/arch/x86/floatregfile.cc
@@ -113,27 +113,27 @@ void FloatRegFile::clear()
FloatReg FloatRegFile::readReg(int floatReg, int width)
{
FloatReg reg = d[floatReg];
- DPRINTF(X86, "Reading %f from register %d.\n", reg, floatReg);
+ DPRINTF(FloatRegs, "Reading %f from register %d.\n", reg, floatReg);
return reg;
}
FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
{
FloatRegBits reg = q[floatReg];
- DPRINTF(X86, "Reading %#x from register %d.\n", reg, floatReg);
+ DPRINTF(FloatRegs, "Reading %#x from register %d.\n", reg, floatReg);
return reg;
}
Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
{
- DPRINTF(X86, "Writing %f to register %d.\n", val, floatReg);
+ DPRINTF(FloatRegs, "Writing %f to register %d.\n", val, floatReg);
d[floatReg] = val;
return NoFault;
}
Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
{
- DPRINTF(X86, "Writing bits %#x to register %d.\n", val, floatReg);
+ DPRINTF(FloatRegs, "Writing bits %#x to register %d.\n", val, floatReg);
q[floatReg] = val;
return NoFault;
}