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authorGabe Black <gblack@eecs.umich.edu>2007-08-29 20:34:52 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-29 20:34:52 -0700
commitbc3635a110747123be066de5238961938ea5df78 (patch)
treed9a4ac053ec78afd29a90f2ad9b82b0b18829a20 /src/arch/x86/floatregfile.hh
parent6204d00940ecae631b040f2b6f46a11eb58cebb6 (diff)
downloadgem5-bc3635a110747123be066de5238961938ea5df78.tar.xz
X86: Flesh out register indexing constants.
--HG-- extra : convert_revision : 56eedc076bbb7962c3976599a15ed93c7cb154c0
Diffstat (limited to 'src/arch/x86/floatregfile.hh')
-rw-r--r--src/arch/x86/floatregfile.hh4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/x86/floatregfile.hh b/src/arch/x86/floatregfile.hh
index 18371280d..282cac796 100644
--- a/src/arch/x86/floatregfile.hh
+++ b/src/arch/x86/floatregfile.hh
@@ -100,7 +100,8 @@ namespace X86ISA
{
std::string getFloatRegName(RegIndex);
- const int NumFloatArchRegs = NumMMXRegs + NumXMMRegs;
+ //Each 128 bit xmm register is broken into two effective 64 bit registers.
+ const int NumFloatArchRegs = NumMMXRegs + 2 * NumXMMRegs;
const int NumFloatRegs = NumFloatArchRegs;
class FloatRegFile
@@ -115,6 +116,7 @@ namespace X86ISA
{
uint64_t q[NumFloatRegs];
double d[NumFloatRegs];
+ float f[NumFloatRegs][2];
};
public: