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| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
| tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/x86/insts/microregop.hh | |
| parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
| download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz | |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/x86/insts/microregop.hh')
| -rw-r--r-- | src/arch/x86/insts/microregop.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh index 1f4eb3981..1accc3555 100644 --- a/src/arch/x86/insts/microregop.hh +++ b/src/arch/x86/insts/microregop.hh @@ -64,7 +64,7 @@ namespace X86ISA OpClass __opClass) : X86MicroopBase(_machInst, mnem, _instMnem, setFlags, __opClass), - src1(_src1.idx), dest(_dest.idx), + src1(_src1.regIdx), dest(_dest.regIdx), dataSize(_dataSize), ext(_ext) { foldOBit = (dataSize == 1 && !_machInst.rex.present) ? 1 << 6 : 0; @@ -90,7 +90,7 @@ namespace X86ISA RegOpBase(_machInst, mnem, _instMnem, setFlags, _src1, _dest, _dataSize, _ext, __opClass), - src2(_src2.idx) + src2(_src2.regIdx) { } |