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authorGabe Black <gblack@eecs.umich.edu>2007-09-19 18:27:55 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-09-19 18:27:55 -0700
commita75b6f51060ceaa52014aa4dd6aadc6ca83365f8 (patch)
treea8da313b6cf771f07ab0e1b795ea6be3137d4e29 /src/arch/x86/insts/microregop.hh
parentf3f3747431e001dc6c80da5b6489516b610c22d6 (diff)
downloadgem5-a75b6f51060ceaa52014aa4dd6aadc6ca83365f8.tar.xz
X86: Move the fp microops to their own file with their own base classes in C++ and python.
--HG-- extra : convert_revision : 9cd223f2005adb36fea2bb56fa39793a58ec958c
Diffstat (limited to 'src/arch/x86/insts/microregop.hh')
-rw-r--r--src/arch/x86/insts/microregop.hh42
1 files changed, 0 insertions, 42 deletions
diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh
index f6bebb763..d805adb33 100644
--- a/src/arch/x86/insts/microregop.hh
+++ b/src/arch/x86/insts/microregop.hh
@@ -62,47 +62,6 @@
namespace X86ISA
{
- namespace ConditionTests
- {
- enum CondTest {
- True,
- NotFalse = True,
- ECF,
- EZF,
- SZnZF,
- MSTRZ,
- STRZ,
- MSTRC,
- STRZnEZF,
- OF,
- CF,
- ZF,
- CvZF,
- SF,
- PF,
- SxOF,
- SxOvZF,
-
- False,
- NotTrue = False,
- NotECF,
- NotEZF,
- NotSZnZF,
- NotMSTRZ,
- NotSTRZ,
- NotMSTRC,
- STRnZnEZF,
- NotOF,
- NotCF,
- NotZF,
- NotCvZF,
- NotSF,
- NotPF,
- NotSxOF,
- NotSxOvZF
- };
- }
-
/**
* Base classes for RegOps which provides a generateDisassembly method.
*/
@@ -136,7 +95,6 @@ namespace X86ISA
uint64_t genFlags(uint64_t oldFlags, uint64_t flagMask,
uint64_t _dest, uint64_t _src1, uint64_t _src2,
bool subtract = false) const;
- bool checkCondition(uint64_t flags) const;
};
class RegOp : public RegOpBase