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author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/x86/insts/static_inst.cc | |
parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/x86/insts/static_inst.cc')
-rw-r--r-- | src/arch/x86/insts/static_inst.cc | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc index ff425f6bf..b9c5486ed 100644 --- a/src/arch/x86/insts/static_inst.cc +++ b/src/arch/x86/insts/static_inst.cc @@ -120,7 +120,7 @@ namespace X86ISA } void - X86StaticInst::printReg(std::ostream &os, int reg, int size) const + X86StaticInst::printReg(std::ostream &os, RegId reg, int size) const { assert(size == 1 || size == 2 || size == 4 || size == 8); static const char * abcdFormats[9] = @@ -132,20 +132,20 @@ namespace X86ISA static const char * microFormats[9] = {"", "t%db", "t%dw", "", "t%dd", "", "", "", "t%d"}; - RegIndex rel_reg; + RegIndex reg_idx = reg.regIdx; - switch (regIdxToClass(reg, &rel_reg)) { + switch (reg.regClass) { case IntRegClass: { const char * suffix = ""; - bool fold = rel_reg & IntFoldBit; - rel_reg &= ~IntFoldBit; + bool fold = reg_idx & IntFoldBit; + reg_idx &= ~IntFoldBit; if (fold) suffix = "h"; - else if (rel_reg < 8 && size == 1) + else if (reg_idx < 8 && size == 1) suffix = "l"; - switch (rel_reg) { + switch (reg_idx) { case INTREG_RAX: ccprintf(os, abcdFormats[size], "a"); break; @@ -195,41 +195,41 @@ namespace X86ISA ccprintf(os, longFormats[size], "15"); break; default: - ccprintf(os, microFormats[size], rel_reg - NUM_INTREGS); + ccprintf(os, microFormats[size], reg_idx - NUM_INTREGS); } ccprintf(os, suffix); break; } case FloatRegClass: { - if (rel_reg < NumMMXRegs) { - ccprintf(os, "%%mmx%d", rel_reg); + if (reg_idx < NumMMXRegs) { + ccprintf(os, "%%mmx%d", reg_idx); return; } - rel_reg -= NumMMXRegs; - if (rel_reg < NumXMMRegs * 2) { - ccprintf(os, "%%xmm%d_%s", rel_reg / 2, - (rel_reg % 2) ? "high": "low"); + reg_idx -= NumMMXRegs; + if (reg_idx < NumXMMRegs * 2) { + ccprintf(os, "%%xmm%d_%s", reg_idx / 2, + (reg_idx % 2) ? "high": "low"); return; } - rel_reg -= NumXMMRegs * 2; - if (rel_reg < NumMicroFpRegs) { - ccprintf(os, "%%ufp%d", rel_reg); + reg_idx -= NumXMMRegs * 2; + if (reg_idx < NumMicroFpRegs) { + ccprintf(os, "%%ufp%d", reg_idx); return; } - rel_reg -= NumMicroFpRegs; - ccprintf(os, "%%st(%d)", rel_reg); + reg_idx -= NumMicroFpRegs; + ccprintf(os, "%%st(%d)", reg_idx); break; } case CCRegClass: - ccprintf(os, "%%cc%d", rel_reg); + ccprintf(os, "%%cc%d", reg_idx); break; case MiscRegClass: - switch (rel_reg) { + switch (reg_idx) { default: - ccprintf(os, "%%ctrl%d", rel_reg); + ccprintf(os, "%%ctrl%d", reg_idx); } break; } @@ -250,14 +250,14 @@ namespace X86ISA { if (scale != 1) ccprintf(os, "%d*", scale); - printReg(os, index, addressSize); + printReg(os, InstRegIndex(index), addressSize); someAddr = true; } if (base != ZeroReg) { if (someAddr) os << " + "; - printReg(os, base, addressSize); + printReg(os, InstRegIndex(base), addressSize); someAddr = true; } } |