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author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/x86/insts/static_inst.hh | |
parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/x86/insts/static_inst.hh')
-rw-r--r-- | src/arch/x86/insts/static_inst.hh | 32 |
1 files changed, 24 insertions, 8 deletions
diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh index d06470a3e..0cea0e132 100644 --- a/src/arch/x86/insts/static_inst.hh +++ b/src/arch/x86/insts/static_inst.hh @@ -51,11 +51,27 @@ namespace X86ISA * wrapper struct for these lets take advantage of the compiler's type * checking. */ - struct InstRegIndex + struct InstRegIndex : public RegId { - RegIndex idx; - explicit InstRegIndex(RegIndex _idx) : idx(_idx) - {} + explicit InstRegIndex(RegIndex _idx) : + RegId(computeRegClass(_idx), _idx) {} + + private: + // TODO: As X86 register index definition is highly built on the + // unified space concept, it is easier for the moment to rely on + // an helper function to compute the RegClass. It would be nice + // to fix those definition and get rid of this. + RegClass computeRegClass(RegIndex _idx) { + if (_idx < FP_Reg_Base) { + return IntRegClass; + } else if (_idx < CC_Reg_Base) { + return FloatRegClass; + } else if (_idx < Misc_Reg_Base) { + return CCRegClass; + } else { + return MiscRegClass; + } + } }; /** @@ -81,7 +97,7 @@ namespace X86ISA void printSegment(std::ostream &os, int segment) const; - void printReg(std::ostream &os, int reg, int size) const; + void printReg(std::ostream &os, RegId reg, int size) const; void printSrcReg(std::ostream &os, int reg, int size) const; void printDestReg(std::ostream &os, int reg, int size) const; void printMem(std::ostream &os, uint8_t segment, @@ -91,7 +107,7 @@ namespace X86ISA inline uint64_t merge(uint64_t into, uint64_t val, int size) const { X86IntReg reg = into; - if (_destRegIdx[0] & IntFoldBit) + if (_destRegIdx[0].regIdx & IntFoldBit) { reg.H = val; return reg; @@ -122,7 +138,7 @@ namespace X86ISA { X86IntReg reg = from; DPRINTF(X86, "Picking with size %d\n", size); - if (_srcRegIdx[idx] & IntFoldBit) + if (_srcRegIdx[idx].regIdx & IntFoldBit) return reg.H; switch(size) { @@ -143,7 +159,7 @@ namespace X86ISA { X86IntReg reg = from; DPRINTF(X86, "Picking with size %d\n", size); - if (_srcRegIdx[idx] & IntFoldBit) + if (_srcRegIdx[idx].regIdx & IntFoldBit) return reg.SH; switch(size) { |