diff options
| author | Nathan Binkert <nate@binkert.org> | 2008-10-21 07:12:53 -0700 |
|---|---|---|
| committer | Nathan Binkert <nate@binkert.org> | 2008-10-21 07:12:53 -0700 |
| commit | 9836d81c2bba97e36c43ca22feee1d51a12ce6ac (patch) | |
| tree | eaa352df03cfe58d315e975bbe2a6384c801f221 /src/arch/x86/interrupts.cc | |
| parent | aac93b7d0ce5e8e0241c7299b49cc59a9d095f3e (diff) | |
| download | gem5-9836d81c2bba97e36c43ca22feee1d51a12ce6ac.tar.xz | |
style: Use the correct m5 style for things relating to interrupts.
Diffstat (limited to 'src/arch/x86/interrupts.cc')
| -rw-r--r-- | src/arch/x86/interrupts.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc index bfb4d5b9c..a16ea5360 100644 --- a/src/arch/x86/interrupts.cc +++ b/src/arch/x86/interrupts.cc @@ -470,7 +470,7 @@ X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) } bool -X86ISA::Interrupts::check_interrupts(ThreadContext * tc) const +X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const { RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); if (pendingUnmaskableInt) { @@ -492,9 +492,9 @@ X86ISA::Interrupts::check_interrupts(ThreadContext * tc) const } Fault -X86ISA::Interrupts::getInterrupt(ThreadContext * tc) +X86ISA::Interrupts::getInterrupt(ThreadContext *tc) { - assert(check_interrupts(tc)); + assert(checkInterrupts(tc)); // These are all probably fairly uncommon, so we'll make them easier to // check for. if (pendingUnmaskableInt) { @@ -523,9 +523,9 @@ X86ISA::Interrupts::getInterrupt(ThreadContext * tc) } void -X86ISA::Interrupts::updateIntrInfo(ThreadContext * tc) +X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) { - assert(check_interrupts(tc)); + assert(checkInterrupts(tc)); if (pendingUnmaskableInt) { if (pendingSmi) { DPRINTF(LocalApic, "SMI sent to core.\n"); |