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authorGabe Black <gblack@eecs.umich.edu>2008-10-12 13:45:21 -0700
committerGabe Black <gblack@eecs.umich.edu>2008-10-12 13:45:21 -0700
commitec9d3aad71ec75b3f7b5ea96dd41f067a9261392 (patch)
treeace8a36db527092dc6bcde234aad5d85c1e20c17 /src/arch/x86/interrupts.hh
parent876f4845f258ed09d348135d8af8cf4a17de1b8a (diff)
downloadgem5-ec9d3aad71ec75b3f7b5ea96dd41f067a9261392.tar.xz
X86: Make the local APIC process interrupts and send them to the CPU.
Diffstat (limited to 'src/arch/x86/interrupts.hh')
-rw-r--r--src/arch/x86/interrupts.hh24
1 files changed, 23 insertions, 1 deletions
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index cfc1ada9d..85a0f6478 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -60,6 +60,7 @@
#include "arch/x86/apicregs.hh"
#include "arch/x86/faults.hh"
+#include "arch/x86/intmessage.hh"
#include "base/bitfield.hh"
#include "cpu/thread_context.hh"
#include "dev/io_device.hh"
@@ -99,6 +100,22 @@ class Interrupts : public BasicPioDevice, IntDev
ApicTimerEvent apicTimerEvent;
/*
+ * A set of variables to keep track of interrupts that don't go through
+ * the IRR.
+ */
+ bool pendingSmi;
+ TriggerIntMessage smiMessage;
+ bool pendingNmi;
+ TriggerIntMessage nmiMessage;
+ bool pendingExtInt;
+ TriggerIntMessage extIntMessage;
+ bool pendingInit;
+ TriggerIntMessage initMessage;
+
+ // This is a quick check whether any of the above (except ExtInt) are set.
+ bool pendingUnmaskableInt;
+
+ /*
* IRR and ISR maintenance.
*/
uint8_t IRRV;
@@ -207,7 +224,12 @@ class Interrupts : public BasicPioDevice, IntDev
*/
Interrupts(Params * p) : BasicPioDevice(p), IntDev(this),
- latency(p->pio_latency), clock(0)
+ latency(p->pio_latency), clock(0),
+ pendingSmi(false), smiMessage(0),
+ pendingNmi(false), nmiMessage(0),
+ pendingExtInt(false), extIntMessage(0),
+ pendingInit(false), initMessage(0),
+ pendingUnmaskableInt(false)
{
pioSize = PageBytes;
memset(regs, 0, sizeof(regs));