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authorGabe Black <gblack@eecs.umich.edu>2007-07-14 17:14:19 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-07-14 17:14:19 -0700
commit4f7809d5e674384f58d3be6f4591afc0ceb2c37e (patch)
treeb776d1916615d67db85e1ccfc4374a52e09b8733 /src/arch/x86/intregs.hh
parent92bb9242fb14db7ce3f78572ea428c8b3c06798a (diff)
downloadgem5-4f7809d5e674384f58d3be6f4591afc0ceb2c37e.tar.xz
Pull some hard coded base classes out of the isa description.
--HG-- rename : src/arch/x86/isa/base.isa => src/arch/x86/isa/outputblock.isa extra : convert_revision : 7954e7d5eea3b5966c9e273a08bcd169a39f380c
Diffstat (limited to 'src/arch/x86/intregs.hh')
-rw-r--r--src/arch/x86/intregs.hh10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/x86/intregs.hh b/src/arch/x86/intregs.hh
index 1b5777f01..c3beb27c3 100644
--- a/src/arch/x86/intregs.hh
+++ b/src/arch/x86/intregs.hh
@@ -58,8 +58,18 @@
#ifndef __ARCH_X86_INTREGS_HH__
#define __ARCH_X86_INTREGS_HH__
+#include "base/bitfield.hh"
+
namespace X86ISA
{
+ BitUnion64(X86IntReg)
+ Bitfield<63,0> R;
+ Bitfield<31,0> E;
+ Bitfield<15,0> X;
+ Bitfield<15,8> H;
+ Bitfield<7, 0> L;
+ EndBitUnion(X86IntReg)
+
enum IntRegIndex
{
INTREG_RAX,