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author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-12-30 12:45:50 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-12-30 12:45:50 -0600 |
commit | e9fa54de58846a8726b9320d6b10809ff65ccecf (patch) | |
tree | 2c7682db49684f8ecf9b303d5f781143f0be9f23 /src/arch/x86/isa.cc | |
parent | 23ba6fc5fbaf55b016b5f0c0a852fa135d3f5f55 (diff) | |
download | gem5-e9fa54de58846a8726b9320d6b10809ff65ccecf.tar.xz |
x86: implement x87 fp instruction fnstsw
This patch implements the fnstsw instruction. The code was originally written
by Vince Weaver. Gabe had made some comments about the code, but those were
never addressed. This patch addresses those comments.
Diffstat (limited to 'src/arch/x86/isa.cc')
-rw-r--r-- | src/arch/x86/isa.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index 0b5523864..5305b1058 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -127,6 +127,13 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc) if (miscReg == MISCREG_TSC) { return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle(); } + + if (miscReg == MISCREG_FSW) { + MiscReg fsw = regVal[MISCREG_FSW]; + MiscReg top = regVal[MISCREG_X87_TOP]; + return (fsw & (~(7ULL << 11))) + (top << 11); + } + return readMiscRegNoEffect(miscReg); } |